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1.发明公开Variable self-correcting digital delay circuit 失效Selbst korrigierender，变量标记数字器Verzögerungsschaltkreis。
公开(公告)号：EP0480860A1
公开(公告)日：1992-04-15
申请号：EP91480146.9
申请日：1991-09-26
IPC分类号： H03K5/135 , H03K19/003 , H03K5/12 , H03K5/13
CPC分类号： H03K19/00323 , H03K5/131 , H03K5/135 , H03K2005/00104 , H03K2005/00247
摘要： A variable self-correcting on-chip circuit comprised of a plurality of digital circuit components is described, whereby electrical signals are precisely positioned with respect to one another. Electrical signals are converted into a number of pulses within a predefined time window. A first number of pulses obtained from free on-chip circuit oscillation is compared to a second number of pulses derived from a predetermined delay defined by the user. An unequal comparison generates control signals capable of advancing or retarding electrical signals. The delay adjustments account for technology, process, temperature and power supply variations. The compounded effect of these variations translates into a certain delay for which self-correction takes effect.
摘要翻译： 描述由多个数字电路部件组成的可变自校正片上电路，由此电信号相对于彼此精确定位。 电信号在预定时间窗口内被转换成多个脉冲。 将从自由片上电路振荡获得的第一数量的脉冲与由用户定义的预定延迟导出的第二数量的脉冲进行比较。 不平等比较产生能够推进或延迟电信号的控制信号。 延迟调整涉及到技术，过程，温度和电源变化。 这些变化的复合效应转化为一定的延迟，自我校正将起作用。
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2.发明公开Apparatus for skew compensating signals 失效Einrichtung zur Erzeugung von Signalen zur Zeitverschiebungskompensation。
公开(公告)号：EP0306662A2
公开(公告)日：1989-03-15
申请号：EP88111128.0
申请日：1988-07-12
申请人： TEKTRONIX, INC.
发明人： Greub, Hans J.
IPC分类号： H03K5/13
CPC分类号： H03K3/0231 , H03K5/133 , H03K2005/00052 , H03K2005/00104 , H03K2005/00176 , H03K2005/00182 , H03K2005/00228
摘要： A clock signal is transmitted to nodes (13) of each of several interconnected circuits (16) through a separate adjustable delay circuit (18), the time delay of each delay circuit being adjusted so that the clock signal arrives at each node (13) at the same time, thereby synchronizing operation of the separate integrated circuits one to another. Each delay circuit (18) comprises a set of signal delay elements which can be selectively switched into the clock signal path so that the clock signal delay may be adjusted by adjusting the number of signal delay elements in the clock signal path. Each signal delay element itself has a unit delay adjustable in proportion to an applied control voltage generated by a delay element monitor (30). The delay element monitor (30) measures the unit delay in relation to the period of a stable reference clock and adjusts the delay of each delay element as necessary to ensure that the unit delay remains constant.
摘要翻译： 通过单独的可调延迟电路（18）将时钟信号发送到几个互连电路（16）中的每一个的节点（13），调整每个延迟电路的时间延迟，使得时钟信号到达每个节点（13） 从而同时分离集成电路的同步操作。 每个延迟电路（18）包括一组信号延迟元件，其可以选择性地切换到时钟信号路径中，从而可以通过调整时钟信号路径中的信号延迟元件的数量来调整时钟信号延迟。 每个信号延迟元件本身具有与由延迟元件监视器（30）产生的施加的控制电压成比例的单位延迟。 延迟元件监视器（30）测量相对于稳定参考时钟的周期的单位延迟，并根据需要调整每个延迟元件的延迟，以确保单位延迟保持恒定。
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公开(公告)号：EP0527366B1
公开(公告)日：1995-09-27
申请号：EP92112549.8
申请日：1992-07-22
发明人： Ochiai, Katsumi
IPC分类号： G01R31/28 , G01R31/3177
CPC分类号： H03K5/131 , G01R31/3191 , G01R31/31922 , G01R31/31926 , H03K2005/00104 , H03K2005/00143
摘要： A plurality of delay stages (21) are connected in cascade, each delay stage having a construction in which either one of a path of a delay element (17) utilizing the propagation delay of a gate array and a path (18) not passing through the delay element is selected by a path selector (19). Each bit of control data is used to control the path selector of the corresponding delay stages. Composite delays are measured for all combinations of such paths, control data (DC) which provides a measured composite delay closest to an intended delay corresponding to each set data (DL) is determined and is prestored in a main conversion table (22). A prediction is made, through calculation, as to a delay for each control data when ambient temperature rises INCREMENT T DEG C from a temperature TO at which the main conversion table was produced, the thus predicted delay is used to determine control data which provides a predicted delay closest to an intended delay for each set data, and the relationship between the control data and the set data is prestored in a corrected conversion table (31, 32). Ambient temperature is detected by temperature detection/control circuit (36). When the difference INCREMENT t between the detected temperature and the temperature tO is INCREMENT t /= INCREMENT T DEG C, control data of the corrected conversion table is selected, and the path selector of each delay stage is controlled accordingly.
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公开(公告)号：EP0527366A1
公开(公告)日：1993-02-17
申请号：EP92112549.8
申请日：1992-07-22
发明人： Ochiai, Katsumi
IPC分类号： G01R31/28 , G01R31/3177
CPC分类号： H03K5/131 , G01R31/3191 , G01R31/31922 , G01R31/31926 , H03K2005/00104 , H03K2005/00143
摘要： A plurality of delay stages (21) are connected in cascade, each delay stage having a construction in which either one of a path of a delay element (17) utilizing the propagation delay of a gate array and a path (18) not passing through the delay element is selected by a path selector (19). Each bit of control data is used to control the path selector of the corresponding delay stages. Composite delays are measured for all combinations of such paths, control data (D C ) which provides a measured composite delay closest to an intended delay corresponding to each set data (D L ) is determined and is prestored in a main conversion table (22). A prediction is made, through calculation, as to a delay for each control data when ambient temperature rises △T°C from a temperature T O at which the main conversion table was produced, the thus predicted delay is used to determine control data which provides a predicted delay closest to an intended delay for each set data, and the relationship between the control data and the set data is prestored in a corrected conversion table (31, 32). Ambient temperature is detected by temperature detection/control circuit (36). When the difference △t between the detected temperature and the temperature t O is △t
摘要翻译： 多个延迟级（21）级联连接，每个延迟级具有利用门阵列的传播延迟的延迟元件（17）的路径和不通过的路径（18）的结构 延迟元件由路径选择器（19）选择。 控制数据的每一位用于控制相应延迟级的路径选择器。 对这种路径的所有组合测量复合延迟，确定提供最接近对应于每个集合数据（DL）的预期延迟的测量复合延迟的控制数据（DC），并将其预存储在主转换表（22）中。 通过计算，当环境温度从产生主转换表的温度T0升高到INCREMENT T°C时，通过计算来预测每个控制数据的延迟，由此预测的延迟用于确定提供 预测延迟最接近于每个设定数据的预期延迟，并且控制数据与设定数据之间的关系预先存储在校正转换表（31,32）中。 环境温度由温度检测/控制电路（36）检测。 当检测温度和温度t0之间的差值INCREMENT t为INCREMENT t
/ = INCREMENT T DEGC时，选择校正的转换表的控制数据，并且相应地控制每个延迟级的路径选择器。 -
5.发明公开Method for operating a programmable delay circuit and programmable delay circuit 失效一种操作可编程延迟电路和可编程延迟电路的方法。
公开(公告)号：EP0394166A2
公开(公告)日：1990-10-24
申请号：EP90480040.6
申请日：1990-03-13
发明人： Fisher, Jeffrey Herbert , Grasso, Lawrence Joseph , Hoffman, Dale Eugene , Skooglund, Daniel Edward , Young, Diane Kay
IPC分类号： H03K5/135
CPC分类号： H03K5/131 , H03K5/135 , H03K2005/00097 , H03K2005/00104 , H03K2005/00247 , H03K2005/00254
摘要： A method of operating a delay circuit to impose a selected delay on an electronic signal, the delay circuit comprising a plurality of delay stages and means for directing the electronic signal through selected ones of the delay stages, the method comprising the steps of: measuring the actual signal delay through each of the delay stages; and selecting, based on the signal delays obtained in the measuring step, the delay stages through which the electronic signal is directed.
摘要翻译： 操作延迟电路的方法，施加到电子信号所选择的延迟，该延迟电路包括延迟级和装置的多个用于通过所述延迟级的所选择的指示电子信号，该方法包括以下步骤：测量所述 通过每个延迟级的实际信号延迟; 选择，并且基于在所述测量步骤中获得的信号延迟，延迟级，通过该电子信号被引导。
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公开(公告)号：EP1410504A2
公开(公告)日：2004-04-21
申请号：EP02736324.1
申请日：2002-05-21
CPC分类号： H03L7/0805 , H03K5/133 , H03K5/135 , H03K2005/00104 , H03L7/07 , H03L7/0812
摘要： The present invention relates in general to the field of generation of precise electrical signals, in particular, to a technique for providing accurate delays of signals using a controllable delay line, and is applicable to the areas of high speed communication and memory testing equipment. According to the present invention, an auxiliary reference channel having a delay line which is identical to the main delay line is incorporated into vernier silicon die to allow automatic adjustment of the delay in the main delay line using a reference periodical signal applied to the auxiliary delay line.
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7.发明公开COMPENSATED DIGITAL DELAY SEMICONDUCTOR DEVICE WITH SELECTABLE OUTPUT TAPS AND METHOD THEREFOR. 失效补偿的数字延时器半导体技术具有可选择的水龙头和使用方法。
公开(公告)号：EP0626112A4
公开(公告)日：1995-02-08
申请号：EP93904874
申请日：1993-02-04
申请人： VLSI TECHNOLOGY INC
发明人： SORRELLS PETER , GERINGER NED
CPC分类号： H03L7/0805 , H03K5/135 , H03K19/00323 , H03K2005/00104 , H03L7/0814
摘要： A compensated digital delay semiconductor device is disclosed which uses two identical chains (10 and 12) of delay elements (14). The first chain is the Reference Chain (10), which is driven by a crystal-controlled digital clock input (17). The second chain is the Input Signal Delay Chain (12), which is the delay path for the signal of interest. These two chains (10 and 12) are located in physical proximity on the semiconductor die so that variations in the manufacturing process, temperature and power supply affect each chain (10 and 12) the same. Circuitry monitors the delay performance of the Reference Chain (10), and dynamically changes the output tap (40, 42, 44, 46, 48, 50, 52, and 54) of the Input Signal Delay Chain (12) when a change in performance is detected on the Reference Chain (10), thereby compensating the delay of the device. This approach provides precise delays which are constant.
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8.发明公开COMPENSATED DIGITAL DELAY SEMICONDUCTOR DEVICE WITH SELECTABLE OUTPUT TAPS AND METHOD THEREFOR 失效补偿的数字延时器半导体技术具有可选择的水龙头和使用方法。
公开(公告)号：EP0626112A1
公开(公告)日：1994-11-30
申请号：EP93904874.0
申请日：1993-02-04
发明人： SORRELLS, Peter , GERINGER, Ned
CPC分类号： H03L7/0805 , H03K5/135 , H03K19/00323 , H03K2005/00104 , H03L7/0814
摘要： Dispositif numérique compensé de temporisation à semiconducteurs utilisant deux chaînes identiques (10 et 12) d'éléments de temporisation (14). La première est la chaîne de référence (10) qui est commandée par une entrée (17) d'horloge numérique pilotée par cristal. La deuxième chaîne est la chaîne de temporisation de signaux d'entrée (12), qui constitue le chemin de temporisation pour les signaux en question. Ces deux chaînes (10 et 12) sont situées à proximité sur la puce de semiconducteurs, de telle sorte que les variations de procédé de production, de température et d'alimentation d'énergie influent de la même façon sur l'une et l'autre (10 et 12). Un circuit permet de contrôler la fonction de temporisation de la chaîne de référence (10) et de modifier dynamiquement la prise de sortie (40, 42, 44, 46, 48, 50, 52, 54) de la chaîne de temporisation de signaux d'entrée (12) lorsqu'une variation dans le fonctionnement est détectée au niveau de la chaîne de référence (10), assurant ainsi la compensation de la temporisation du dispositif. Ce système permet d'obtenir des temporisations précises et constantes.
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公开(公告)号：EP0306662B1
公开(公告)日：1992-09-02
申请号：EP88111128.0
申请日：1988-07-12
申请人： TEKTRONIX, INC.
发明人： Greub, Hans J.
IPC分类号： H03K5/13
CPC分类号： H03K3/0231 , H03K5/133 , H03K2005/00052 , H03K2005/00104 , H03K2005/00176 , H03K2005/00182 , H03K2005/00228
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公开(公告)号：EP2095506A2
公开(公告)日：2009-09-02
申请号：EP07864266.7
申请日：2007-11-12
CPC分类号： H03K5/131 , H03K2005/00104 , H03K2005/00156
摘要： A tunable delay line is calibrated to maintain the delay of the delay line at a desired value or within a desired range of values. In some aspects a signal is passed through a delay line multiple times so that the cumulative delay of the signal through the delay line (e.g., as indicated by a count) may be calculated over a period of time. The count is compared with an expected count and, based on this comparison, the delay of the delay line is adjusted as necessary. In some aspects the signal may comprise a digital signal. In some aspects a delay through a delay line may be calculated based on analysis of amplitude changes in a signal caused by a phase shift imparted on the signal by the delay line. In some aspects a delay line is incorporated into a transmitted reference system to generate and/or process transmitted reference signals.
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