公开(公告)号：EP3384422B1

公开(公告)日：2021-02-24

申请号：EP16871511.8

申请日：2016-12-01

发明人： HUTTER, Michael ,  BAKER, Matthew

IPC分类号： H04L9/00 ,  G06F21/55 ,  G06F21/72 ,  G06K19/073 ,  G06F21/75 ,  G01R31/317 ,  G01R31/3177 ,  G09C1/00

公开(公告)号：EP3105674B1

公开(公告)日：2018-01-10

申请号：EP13817757.1

申请日：2013-11-28

申请人： Telefonaktiebolaget LM Ericsson (publ)

发明人： SELANDER, Göran ,  NÄSLUND, Mats ,  DUBROVA, Elena

IPC分类号： G01R31/3185 ,  G01R31/317 ,  G06F7/58 ,  G01R31/3181 ,  G11C19/00 ,  G01R31/3177 ,  G11C19/28 ,  G11C29/02

CPC分类号： G01R31/31703 ,  G01R31/31723 ,  G01R31/3177 ,  G01R31/31813 ,  G01R31/318547 ,  G11C19/28 ,  G11C29/02 ,  G11C29/021

摘要： A Feedback Shift-Register (FSR) enabling improved testing, e.g., Built-In Self-Tests (BIST), is provided. Each cell of the FSR may either be an observable cell, associated with a non-trivial feedback function implemented by a combinational logic circuit, or a controllable cell, having an associated state variable which belongs to the dependence set of exactly one of the non-trivial feedback functions. Each controllable cell is provided with a multiplexer for selecting either a predecessor cell of the controllable cell or a test value as input. Thus, the sequential circuit of the FSR in an embodiment is tested using tests for combinational logic. The disclosed test procedures utilize a minimal set of test vectors and allow detection of all single stuck-at faults in the FSR. The resulting dynamic power dissipation during test can be considerably less than known BIST designs.

公开(公告)号：EP2614380B1

公开(公告)日：2015-08-19

申请号：EP11824099.3

申请日：2011-09-08

申请人： Lexmark International, Inc.

发明人： BAILEY, James, Ray ,  CASE, Christopher, Wilson ,  SHARPE, James, Patrick

IPC分类号： G01R31/28 ,  G01R31/3177 ,  G06F11/22

CPC分类号： G01R31/3177 ,  G06F11/2294

公开(公告)号：EP2677328B1

公开(公告)日：2015-07-29

申请号：EP13185427.5

申请日：2007-02-19

申请人： Mentor Graphics Corporation

发明人： Mrugalski, Grzegorz ,  Rajski, Janusz ,  Tyszer, Jerzy ,  Cheng, Wu-tung ,  Mukherjee, Nilanjan ,  Kassab, Mark

IPC分类号： G01R31/3185 ,  G06F11/267 ,  G01R31/3177

CPC分类号： G01R31/3177 ,  G01R31/2851 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318547 ,  G01R31/318563 ,  G01R31/318566

摘要： Disclosed herein are exemplary embodiments of a so-called "X-press" test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000x. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

公开(公告)号：EP1922555B1

公开(公告)日：2014-10-08

申请号：EP06789621.7

申请日：2006-08-09

申请人： Texas Instruments Incorporated

发明人： WHETSEL, Lee, D.

IPC分类号： G01R31/3177 ,  G01R31/3185

CPC分类号： G01R31/31723 ,  G01R31/31722 ,  G01R31/31725 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318572 ,  G06F11/261 ,  G06F11/267 ,  G06F11/27 ,  G06F11/3466

摘要： An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and TDI input from a single data pin. After being enabled, the Trace domain acquires data from a functioning circuit within the IC in response to a first clock and outputs the acquired data from the IC in response to a second clock. An addressable two pin interface loads and updates instructions and data to a TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation. Trace circuitry within an IC can operate autonomously to store and output functional data occurring in the IC. The store and output operations of the trace circuitry are transparent to the functional operation of the IC. An auto-addressing RAM memory stores input data at an input address generated in response to an input clock, and outputs stored data from an output address generated in response to an output clock.

公开(公告)号：EP2211191A3

公开(公告)日：2012-06-20

申请号：EP10250061.8

申请日：2010-01-14

申请人： Tektronix, Inc.

发明人： Stoops, John F. ,  Knierim, Daniel G.

IPC分类号： G01R31/3177

CPC分类号： H03K5/2481 ,  G01R13/0254 ,  G01R31/3177

摘要： A test and measurement instrument (90) includes acquisition circuitry (92) configured to acquire a plurality of data signals; a plurality of word recognizer elements (60,96), each word recognizer element configured to compare a corresponding one of the data signals (D,D 0 -D N-1 ) with a desired data bit and each word recognizer element having a delay less than or equal to about one gate delay; logic circuitry (98) to combine outputs of the word recognizer elements; and trigger circuitry (100) responsive to the logic circuit.

摘要翻译： 测试和测量仪器（90）包括被配置为获取多个数据信号的采集电路（92） 多个字识别器元件（60,96），每个字识别器元件被配置为将数据信号（D，D 0 -D N-1）中的相应一个与期望数据位进行比较，并且每个字识别器元件具有延迟 小于或等于约一个门延迟; 逻辑电路（98）组合所述单词识别器元件的输出; 以及响应逻辑电路的触发电路（100）。

公开(公告)号：EP2060925A2

公开(公告)日：2009-05-20

申请号：EP08253609.5

申请日：2008-11-05

申请人： TEKTRONIX, INC.

发明人： Acuff, Ronald A. ,  Larson, Lester L. ,  Cosgrove, Kevin E.

IPC分类号： G01R31/319 ,  G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/3177 ,  G01R31/3191 ,  G06F11/25

摘要： A test and measurement instrument and a method of calibrating the test and measurement instrument including a reference signal generator (12); multiple input channels (14); and multiple input circuits (16). Each input channel is coupled to a corresponding input circuit; and one of the input circuits is coupled to the reference signal generator.

摘要翻译： 一种测试和测量仪器以及校准包括参考信号发生器（12）的测试和测量仪器的方法; 多个输入通道（14）; 和多个输入电路（16）。 每个输入通道耦合到相应的输入电路; 并且其中一个输入电路耦合到参考信号发生器。

公开(公告)号：EP1783505A1

公开(公告)日：2007-05-09

申请号：EP06255631.1

申请日：2006-11-01

申请人： Tektronix, Inc.

发明人： Sullivan, Steven K. ,  Dobyns, Kenneth P.

IPC分类号： G01R31/3177

CPC分类号： H03M7/3066 ,  G01R31/31921

摘要： A test and measurement instrument samples an input digital logic signal to produce logic samples, compresses the logic samples into compression codes, and stores the compression codes into acquisition memory. Compression includes parsing the logic samples into groups and assigning compression codes to those groups, and is performed so as not to lose information about the input digital logic signal's activity. The instrument converts the stored compression codes into a waveform image in display memory and displays the stored waveform image on a display device.

摘要翻译： 测试和测量仪器对输入数字逻辑信号进行采样以产生逻辑采样，将逻辑采样压缩为压缩代码，并将压缩代码存储到采集存储器中。 压缩包括将逻辑样本解析成组并将压缩代码分配给这些组，并且被执行以便不丢失关于输入数字逻辑信号的活动的信息。 仪器将存储的压缩码转换为显示存储器中的波形图像，并将显示的存储的波形图像显示在显示设备上。

公开(公告)号：EP1480050A3

公开(公告)日：2005-06-01

申请号：EP04252666.5

申请日：2004-05-07

申请人： Tektronix Inc.

发明人： Hagen, Michael S. ,  Spisak, Kevin C.

IPC分类号： G01R31/319 ,  G06F11/25 ,  G01R31/3177

CPC分类号： G01R31/3177 ,  G01R31/31926 ,  G06F11/25

摘要： A plurality of digital samplers operating on a common signal under test (SUT) sample the SUT at a sample rate beyond that which guarantees monotonic sampling and non-overlapping setup and hold windows for adjacent samplers. Subsequent processing of the sample streams restores monotonicity and sample independence to provide thereby a very high effective sample rate.

公开(公告)号：EP1293790A1

公开(公告)日：2003-03-19

申请号：EP01307925.6

申请日：2001-09-18

申请人： STMicroelectronics Limited

发明人： Warren, Robert Geoffrey

IPC分类号： G01R31/3185 ,  G01R31/3177

CPC分类号： G01R31/318552 ,  G01R31/31937

摘要： The invention discloses a system comprising a host, a target and connection means therebetween. The host has means for providing a clock signal, first output means for outputting said clock signal to said target via said connection means and second output means for outputting data to said target via said connection means, said data being clocked out by said clock signal, said target having first input means for receiving said clock signal from said host, second input means for receiving said data from said host and first output means for outputting data to said host via said connection means. The host further comprises input means for receiving said data from said target, and oversampling means for oversampling the received data from the target and controlling the clocking in of said data received from said target in dependence on said oversampling.

摘要翻译： 本发明公开了一种包括主机，目标和它们之间的连接装置的系统。 主机具有用于提供时钟信号的装置，用于经由所述连接装置将所述时钟信号输出到所述目标的第一输出装置和用于经由所述连接装置将数据输出到所述目标的第二输出装置，所述数据由所述时钟信号计时， 所述目标具有用于从所述主机接收所述时钟信号的第一输入装置，用于从所述主机接收所述数据的第二输入装置和用于经由所述连接装置向所述主机输出数据的第一输出装置。 主机还包括用于从所述目标接收所述数据的输入装置，以及过采样装置，用于对来自目标的接收数据进行过采样，并根据所述过采样控制从所述目标接收到的数据的时钟。