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368 条记录 (耗时 0.014 秒)

    Computer system and method of modifying program in the computer system
    81.
    发明公开
    Computer system and method of modifying program in the computer system 有权
    设备和方法，用于在计算机系统中的程序变更

    公开(公告)号：EP0947920A3

    公开(公告)日：2000-10-25

    申请号：EP99106560.8

    申请日：1999-03-30

    申请人： SANYO ELECTRIC Co., Ltd.

    发明人： Ogata, Hitoshi

    IPC分类号： G06F9/44 ,  G06F9/42 ,  G06F9/26

    CPC分类号： G06F8/60

    摘要： A computer system comprises a microcomputer (20) and external memory means in communication with the microcomputer (20) for storing various programs and various items of data. The microcomputer (20) comprises a nonerasable ROM (22) having stored therein a basic program and basic data indispensable to the operation of the system, a RAM (23) for storing various programs or various kinds of data, a CPU (21) for executing programs and processing data, and an interface circuit for providing communications with external devices. The external memory means has stored therein a modification program for modifying a portion of program data contained in the basic program, and a modification starting address indicating a location in the basic program where the modification of the basic program by the modification program is to be started. The CPU (21) has an address interrupt function for processing an interrupt at a predetermined interrupt address. The microcomputer (20) modifies the basic program by transferring the modification program from the external memory means to the RAM (23), storing the modification starting address in the CPU (21) as the interrupt address, and executing a command to jump to a head address of the modification program in the RAM (23) for an address interrupt.

    AN INSTRUCTION DECODER
    82.
    发明公开
    AN INSTRUCTION DECODER 审中-公开
    INSTRUKTIONSDEKODIERER

    公开(公告)号：EP1034472A2

    公开(公告)日：2000-09-13

    申请号：EP98960140.6

    申请日：1998-12-02

    申请人： Telefonaktiebolaget L M Ericsson (Publ)

    发明人： ROOS, Tobias ,  HALVARSSON, Dan ,  JONSSON, Tomas

    IPC分类号： G06F9/26 ,  G06F9/32

    CPC分类号： G06F9/30181 ,  G06F9/261 ,  G06F9/30145 ,  G06F9/30189 ,  G06F9/30196 ,  G06F11/3024 ,  G06F11/3055 ,  G06F11/3466

    摘要： In a computer system the instruction decoding unit for translating program instructions to microcode instructions operates dynamically. Thus the unit receives state signals indicating the state of the computer, such as a trace enabling signal (63), influencing the translation process in the instruction decoding unit. These state signals (63) are added to the operation code (65) of the program instruction to be decoded, the operation code of the program instruction thus being extended and used as input to a translating table (55), the extended operation code of the program instruction being taken as an address of a field in the table. The addresses and thus the contents of the fields addressed for the same operation code of a program instruction can then be different for different values of the state signals. Thus generally, the state signals cause the instruction decoder to change its translating algorithm so that the decoder can decode an operation code differently depending on the state which the signals adopt. The dynamic decoding can for a trace enabling signal be used for switching on and off a trace function. In the normal case, when tracing is not desired, no microinstructions supporting the trace function have to be executed and thereby the performance and in particular the speed of the computer system will be increased.

    A method and apparatus for operation control of memories
    83.
    发明公开
    A method and apparatus for operation control of memories 失效
    用于控制存储器的操作的方法和装置

    公开(公告)号：EP0831397A3

    公开(公告)日：1999-12-15

    申请号：EP97307347.1

    申请日：1997-09-22

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Leung, Yu-Ying Jackson

    IPC分类号： G06F9/26 ,  G11C16/06

    CPC分类号： G11C29/16

    摘要： The memory control this invention includes a microprogram-read-only-memory (CROM) containing micro-instructions for operation of an integrated-circuit memory, a program counter multiplexer (PCM) to select instructions from the control-read-only-memory, a micro-instruction decoder with BILBO control (MID/BC), a test input multiplexer (TIM) to test control signals, an optional status output register (SOR) to generate control signals, and a subroutine stack (SS) to allow function calls. A program counter (PC) takes an index signal from the micro-instruction decoder with BILBO control (MID/BC) and a signal from the program counter multiplexer (PCM), and from those signals, generates a next microcode address. Complex program, erase, and compaction instructions for the integrated-circuit memory are implemented using a relatively small number of control-read-only-memory locations and using a relatively small surface area on the memory chip. Control instructions are easily modified to compensate for process and structure enhancements are made during the production lifetime of an integrated-circuit memory.

    Semiconductor memory
    85.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：EP0482928B1

    公开(公告)日：1998-07-22

    申请号：EP91309840.6

    申请日：1991-10-24

    申请人： NEC CORPORATION

    发明人： Henmi, Toru, c/o NEC Corporation

    IPC分类号： G06F11/00 ,  G06F11/20 ,  G06F9/26 ,  G06F12/06

    CPC分类号： G06F11/3648 ,  G06F11/1052 ,  G11C29/76

    摘要： A semiconductor memory includes a main PROM (10) for storing main data, an error correcting PROM (20) for storing correcting data, and an error correcting circuit (24) for correcting the main data with the correcting data. A control register (22) supplies a control signal to the error correcting circuit. Error correction by the correcting circuit is halted during the debugging of a program by an "invalid" control signal to avoid the danger of faulty data being supplied from the semiconductor memory.

    Control system for processor
    87.
    发明公开
    Control system for processor 失效
    SteuerungssystemfürProzessor

    公开(公告)号：EP0725333A3

    公开(公告)日：1998-05-06

    申请号：EP96300731

    申请日：1996-01-31

    申请人： NOKIA MOBILE PHONES LTD

    发明人： HAGQVIST JARI ,  RANTA JUKKA

    IPC分类号： G06F9/06 ,  G06F9/26

    CPC分类号： G06F9/328 ,  G06F9/268

    摘要： A computer controlled apparatus includes a program counter for manifesting program count values and a processor for executing a prestored program in accordance with the program count values. The apparatus includes a read only memory with a prestored program that is accessible in response to generation of a span of program count values. Auxiliary memory includes a prestored program segment. A control circuit is coupled to the program counter and stores a predetermined program count value within the span of program count values in ROM. The control circuit is responsive to a match of a program count value from the program counter and the determined program count value to cause the program counter to be loaded with a branch program count value. That value enables the processor to immediately access and execute the prestored program segment from the auxiliary memory in lieu of a subspan of program count addresses in the ROM. The processor responds to the branch program count value as though it is a next program count value from a previous program count value, thereby seamlessly executing the second prestored program.

    摘要翻译： 计算机控制装置包括用于显示程序计数值的程序计数器和用于根据程序计数值执行预存储程序的处理器。 该装置包括只读存储器，其具有可响应于程序计数值的跨度的生成而可访问的预存储程序。 辅助存储器包括预先存储的程序段。 控制电路耦合到程序计数器，并将预定的程序计数值存储在ROM中的程序计数值的范围内。 控制电路响应来自程序计数器的程序计数值和确定的程序计数值的匹配，以使程序计数器加载分支程序计数值。 该值使处理器能够立即从辅助存储器访问并执行预先存储的程序段，代替ROM中的程序计数地址的子跨段。 处理器响应于分支程序计数值，如同它是来自先前程序计数值的下一程序计数值一样，从而无缝地执行第二预存储程序。

    Data processing method and apparatus
    88.
    发明公开
    Data processing method and apparatus 失效
    Datenverarbeitungsverfahren und -vorrichtung

    公开(公告)号：EP0817013A2

    公开(公告)日：1998-01-07

    申请号：EP97110521.8

    申请日：1997-06-26

    申请人： NEC CORPORATION

    发明人： Ienaga, Takashi

    IPC分类号： G06F9/445 ,  G06F9/26 ,  G06F11/20 ,  G06F12/06

    CPC分类号： G06F9/30043 ,  G06F12/0638

    摘要： A data processing apparatus and a data processing method for implementing data-tuning rapidly, in which when CPU is operating based on PROM data, it permits operation to implement while referring to data which is rewritten to RAM without stop of the operation. There is provided a CPU core for performing program operation for the purpose of implementing of data processing, a PROM for storing data which is referred at the time of data processing, a register for memorizing a data-stored-address, and a comparator for comparing an address. The comparator is brought into effective when the data-stored-address is outputted while rewriting the RAM during executing the CPU core, comparing the data-stored-address memorized within the register with an address outputted from the CPU core, bringing the RAM selection signal into active when both correspond with each other, while bringing the PROM selection signal into inactive, after receiving thereof the CPU core refers to the data stored within the RAM instead of the data stored within the non-volatile memory, thereby a data-tuning is capable of being realized without stop of operation.

    摘要翻译： 一种用于快速实现数据调谐的数据处理装置和数据处理方法，其中当CPU基于PROM数据进行操作时，它允许在参考在RAM中重写的数据而实现操作而不停止该操作。 提供了用于执行数据处理的程序操作的CPU内核，用于存储数据处理时参考的数据的PROM，用于存储数据存储地址的寄存器和用于比较的比较器 一个地址 当在执行CPU核心期间重写RAM时输出数据存储地址，比较寄存器中存储的数据存储地址与从CPU核心输出的地址，使RAM选择信号 当两者都相互对应时，在将PROM选择信号置为非活动状态的同时，在接收到它之后，CPU内核是指存储在RAM内的数据而不是存储在非易失性存储器中的数据，因此数据调整是 能够实现而不停止操作。