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    Method and system for executing operations on denormalised numbers
    82.
    发明公开
    Method and system for executing operations on denormalised numbers 审中-公开
    Verfahren und System zurAusführungvon Operationen auf denormalisierten Zahlen

    公开(公告)号：EP0901067A2

    公开(公告)日：1999-03-10

    申请号：EP98306442.9

    申请日：1998-08-12

    申请人： International Business Machines Corporation

    发明人： Schwarz, Eric Mark ,  Giamei, Bruce ,  Krygowski, Christopher ,  Check, Mark Anthony ,  Liptay, John Stephen

    IPC分类号： G06F5/01

    CPC分类号： G06F5/012 ,  G06F9/3861 ,  G06F9/3875 ,  G06F2207/3884

    摘要： A method and system for processing instructions in a floating point unit for executing denormalized numbers in floating point pipeline via serializing uses an instruction unit and having a control unit and a pipelined data flow unit, a shifter and a rounding unit. The floating point unit has an external feedback path for providing intermediate result data from said rounding unit to an input of the pipelined data flow unit to reuse the pipeline for denormalization by passing intermediate results in the pipeline which have a denormalized condition computed after the exponent calculation of the shifting circuit directly from the rounding unit to the top of the dataflow in the pipeline via an external feedback path. The pipelined has two paths which are selected based on the presence of other instructions in the pipeline. If no other instructions are in the pipeline a first path is taken which uses the external feedback path from the rounding unit back into the top of the dataflow. When there are instructions in the pipeline a shifter unit performing normalization of the fraction indicates possible underflow of the exponent, and prepares to hold the exponent and the fraction in a floating point data flow register; and upon detection of exponent underflow during the rounder stage and detection of any other instructions in pipeline; then the control unit forces an interrupt for serialization, and cancels execution of this instruction and other instructions in pipeline.

    摘要翻译： 用于处理浮点单元中的指令的方法和系统，用于通过串行化来执行浮点流水线中的非规范化数字，使用指令单元并具有控制单元和流水线数据流单元，移位器和舍入单元。 浮点单元具有用于将来自所述四舍五入单元的中间结果数据提供给流水线数据流单元的输入的外部反馈路径，以通过将具有在指数计算之后计算的非归一化状态的流水线中的中间结果重新使用来进行非规范化 的移位电路通过外部反馈路径直接从舍入单元到流水线中的数据流的顶部。 流水线有两条路径，这些路径是根据流水线中其他指令的存在而选择的。 如果没有其他指令在流水线中，则采用第一路径，其使用从舍入单元返回到数据流的顶部的外部反馈路径。 当在流水线中存在指令时，执行分数的归一化的移位单元指示指数的可能下溢，并准备保持指数和分数在浮点数据流寄存器中; 并在检测到倒圆阶段期间的指数下溢和检测管道中的任何其他指令时; 那么控制单元强制中断进行串行化，并取消执行该指令和其他指令。

    Digital microprocessor device having variable-delay division hardware
    84.
    发明公开
    Digital microprocessor device having variable-delay division hardware 失效
    具有可变延迟分配硬件的数字微处理器设备

    公开(公告)号：EP0809179A3

    公开(公告)日：1997-12-29

    申请号：EP97302938

    申请日：1997-04-30

    申请人： LUCENT TECHNOLOGIES INC

    IPC分类号： G06F7/537 ,  G06F5/01 ,  G06F7/52 ,  G06F7/535

    CPC分类号： G06F7/535 ,  G06F5/01 ,  G06F2207/5353

    摘要： The present invention is a variable-delay division (VDD) scheme implementable in hardware to execute signed and unsigned integer division and remainder operations in digital processor. The VDD scheme advantageously uses hardware utilized for multiplication to implement a 2-bits/cycle alignment step to iteratively align the divisor with the dividend. This speeds up the alignment phase of integer division. Quotient bits are produced at the rate of 1-bit/cycle using the well-known restoring scheme. For 32-bit 2's complement operands, the scheme has a delay less than a fixed-delay scheme for most operands.

    摘要翻译： 本发明是可用硬件实现的可变延迟分割（VDD）方案，以执行数字处理器中的带符号和无符号整数除法和余数运算。 VDD方案有利地使用用于乘法的硬件来实现2比特/周期对准步骤以迭代地将除数与除数对齐。 这加快了整数除法的对齐阶段。 使用众所周知的恢复方案以1位/周期的速率产生商数位。 对于32位2的补码操作数，对于大多数操作数，该方案的延迟小于固定延迟方案。

    Combined multiplier/shifter and method therefor
    85.
    发明公开
    Combined multiplier/shifter and method therefor 失效
    Kombinierter Multiplizierer / Versbles和Verfahren dazu。

    公开(公告)号：EP0685786A1

    公开(公告)日：1995-12-06

    申请号：EP95107581.1

    申请日：1995-05-18

    申请人： MOTOROLA, INC.

    发明人： Shankar, Ravi ,  Leon, Ana S. ,  Chau-Lee, Kin Ki

    IPC分类号： G06F7/48 ,  G06F5/01 ,  G06F7/52

    CPC分类号： G06F7/5338 ,  G06F5/015 ,  G06F7/57

    摘要： A combined multiplier/shifter (150) uses an existing high-speed multiplier (55) to perform both multiplies and programmable left and right shifts without a dedicated high-speed shifter. A shift decoder (160) used in a shift mode provides first recoded signals according to a shift count and a shift direction. A recoder (161) recodes a multiplier input in a multiply mode to provide second recoded signals. A multiplier array (163) receives either a multiplicand or a shift operand at its multiplicand input, and uses either the first or second recoded signals selectively according to the mode. An output of the multiplier array (163) is either a product in the multiply mode or a first shift result in the shift mode. An output shifter (157) selectively adjusts the first shift result according to the shift direction to provide a second, final shift result.

    摘要翻译： 组合乘法器/移位器（150）使用现有的高速乘法器来执行乘法和可编程的左右移位，而不需要专用的高速移位器。 在移位模式中使用的移位解码器（160）根据移位计数和移位方向提供第一重新编码的信号。 重新编码器（161）以乘法模式重新编码乘法器输入以提供第二重新编码的信号。 乘法器阵列（163）在其被乘数输入处接收被乘数或移位操作数，并且根据该模式选择性地使用第一或第二重新编码信号。 乘法器阵列（163）的输出是乘法模式中的乘积或移位模式的第一移位。 输出移位器（157）根据移位方向选择性地调整第一移位结果以提供第二最终移位结果。

    Shift and rounding circuit and method
    86.
    发明公开
    Shift and rounding circuit and method 失效
    Schaltung und Verfahren zur Verschiebung und Abrundung。

    公开(公告)号：EP0655675A1

    公开(公告)日：1995-05-31

    申请号：EP94110670.0

    申请日：1994-07-08

    申请人： Hewlett-Packard Company

    发明人： Lee, Ruby Bei-Loh

    IPC分类号： G06F5/01 ,  G06F7/48

    CPC分类号： G06F5/01 ,  G06F7/48 ,  G06F7/49952 ,  G06F7/49963

    摘要： A circuit[100] for shifting the bits of an X word to obtain a Y word which is rounded to the nearest odd integer if any bit having the value 1 was shifted off of the word during the shifting operation. The circuit avoids biasing in the integer rounding operation. The shifting operations are accomplished with the aid of multiplexing circuits[101-105]. The rounding operation is accomplished with the aid of multiplexing circuits[105] that connect the least significant bit of Y to (X₀ OR X₁ OR ...X m ), where m is the number of places by which X is shifted.

    摘要翻译： 一个用于移位X字的位的电路[100]，以获得一个Y字，该Y字被舍入到最近的奇整数，如果任何具有值1的位在移位操作期间被偏离了该字。 电路避免整数舍入操作中的偏置。 借助于复用电路[101-105]来实现移位操作。 借助于将Y的最低有效位连接到（X0 OR X1 OR ... Xm）的多路复用电路[105]来完成舍入操作，其中m是X移位的位置数。

    High-speed barrel shifter
    88.
    发明公开
    High-speed barrel shifter 失效
    Schnelle Trommelverschieber。

    公开(公告)号：EP0602337A1

    公开(公告)日：1994-06-22

    申请号：EP93115974.3

    申请日：1993-10-04

    申请人： MOTOROLA, INC.

    发明人： Dang, Keith D. ,  Anderson, Donald C.

    IPC分类号： G06F5/01

    CPC分类号： G06F5/015

    摘要： A high-speed barrel shifter (20) includes a shifter array (25) having a matrix of transistors (40) located at intersections of rows and columns of the matrix (40). The rows and columns alternately function as source and destination terminals. A data-dependent fill portion (48) fills a data-dependent value such as a sign bit into vacated bit positions along rows in a bottom left portion (42). Thus the barrel shifter (20) performs a data-dependent fill instruction within the shifter array (25) and avoids extra clock cycles associated with post-array processing. In one embodiment, an isolation portion (44, 45) separates a top right portion (41) of the matrix (40) from the bottom left portion (42) along a diagonal (43). The isolation portion (44, 45) isolates transistors in the bottom left portion (42), which are associated with rotates and fills, from transistors in the top right portion (41), which are associated with shifts, according to the direction of the shift.

    摘要翻译： 高速桶形移位器（20）包括具有位于矩阵（40）的行和列的相交处的晶体管（40）的矩阵的移位器阵列（25）。 行和列交替地作为源和目标终端。 依赖于数据的填充部分（48）将诸如符号位之类的数据相关值填充到沿左下部分（42）中的排的空位位置。 因此，桶形移位器（20）在移位器阵列（25）内执行与数据相关的填充指令，并避免与后阵列处理相关联的额外的时钟周期。 在一个实施例中，隔离部分（44,45）沿着对角线（43）将矩阵（40）的右上部分（41）与左下部分（42）分开。 隔离部分（44,45）根据与该移位相关联的顶部右侧部分（41）中的晶体管将与左旋部分相关联的左下部分（42）中的晶体管与移位相关联， 转移。