公开(公告)号：EP3361422A1

公开(公告)日：2018-08-15

申请号：EP18156667.0

申请日：2018-02-14

申请人： Google LLC

发明人： Gulland, William John

IPC分类号： G06N3/063

CPC分类号： G06N3/04 ,  G06F5/012 ,  G06F7/483 ,  G06F2207/3824 ,  G06F2207/4824 ,  G06N3/063 ,  G06N3/08

摘要： Methods, systems, and computer storage media for implementing neural networks in fixed point arithmetic computing systems. In one aspect, a method includes the actions of receiving a request to process a neural network using a processing system that performs neural network computations using fixed point arithmetic; for each node of each layer of the neural network, determining a respective scaling value for the node from the respective set of floating point weight values for the node; and converting each floating point weight value of the node into a corresponding fixed point weight value using the respective scaling value for the node to generate a set of fixed point weight values for the node; and providing the sets of fixed point floating point weight values for the nodes to the processing system for use in processing inputs using the neural network.

公开(公告)号：EP1220086A3

公开(公告)日：2002-07-17

申请号：EP01130114.0

申请日：2001-12-18

申请人： NEC CORPORATION

发明人： Sato, Shoichiro, NEC IC Microcomputer Systems,Ltd.

IPC分类号： G06F7/50

CPC分类号： G06F7/49952 ,  G06F5/012

摘要： In a shift and shift-out detecting circuit, a plurality of partial shift circuits respectively have bit shift quantities which are different from each other, and are connected in series. Each of the plurality of partial shift circuits receives a shift result as a previous shift result from the partial shift circuit of a previous stage and a corresponding shift instruction, shifts the previous shift result by the corresponding bit shift quantity in response to the shift instruction to produce a current shift result, and outputs the current shift result to the partial shift circuit of a subsequent stage. A plurality of shift-out detecting circuits are respectively provided for the plurality of partial shift circuits. Each of the plurality of shift-out detecting circuits detects a shift-out of "1" bit from the current shift result and the corresponding shift instruction and generates a partial sticky signal when the shift-out is detected. A collecting circuit collects the partial sticky signals from the plurality of shift-out detecting circuits and generates a sticky signal to indicate generation of the shift-out.

公开(公告)号：EP0361886B1

公开(公告)日：1995-11-29

申请号：EP89309826.9

申请日：1989-09-27

申请人： DATA GENERAL CORPORATION

发明人： Gelinas, Robert G. ,  Radogna, Thomas V.

IPC分类号： G06F7/50 ,  G06F5/01

CPC分类号： G06F7/485 ,  G06F5/012 ,  G06F7/4873 ,  G06F7/535 ,  G06F7/5375 ,  G06F2207/3844

公开(公告)号：EP0233635B1

公开(公告)日：1994-02-02

申请号：EP87102242.2

申请日：1987-02-17

申请人： NEC CORPORATION

发明人： Nukiyama, Tomoji

IPC分类号： G06F5/00

CPC分类号： G06F5/015 ,  G06F5/012

公开(公告)号：EP0474247A3

公开(公告)日：1993-04-07

申请号：EP91115107.4

申请日：1991-09-06

申请人： NEC CORPORATION

发明人： Ishihara, Shingo

IPC分类号： G06F5/01 ,  G06F7/50

CPC分类号： G06F7/485 ,  G06F5/012

摘要： In a floating-point arithmetic unit for performing floating-point arithmetic of first and second input data which are represented by a floating-point representation and composed of first and second exponent parts and first and second mantissa parts, a shift amount calculating circuit comprises first and second subtracters (26, 27) supplied with lower (n + 1) bits of the first and the second exponent parts. The first subtracter subtracts a first lower number (#EA1) from a second lower number (#EB1) to produce a first difference signal (RS1). The second subtracter subtracts the second lower number (#EB1) from the first lower number (#EA1) to produce a second difference signal (RS1). Supplied with the first and the second exponent parts, an exponent comparing unit (28) compares the first exponent part with the second exponent part to produce a comparison result signal (CP1, CP2, CP3, CP4). Responsive to the comparison result signal, a first selector (31) selects one of the first difference signal and first and second value signals ("0", "64") as a first right-shift amount signal (SD1). Responsive to the comparison result signal, a second selector (32) selects one of the second difference signal and the first and the second value signals as a second right-shift amount signal (SD2).

公开(公告)号：EP0362580A3

公开(公告)日：1991-10-30

申请号：EP89116899.9

申请日：1989-09-13

申请人： International Business Machines Corporation

发明人： Hokenek, Erdem ,  Montoye, Robert Kevin

IPC分类号： G06F5/01 ,  G06F7/48

CPC分类号： G06F7/74 ,  G06F5/012

摘要： A method and system are disclosed for performing a leading 0/1 an­ticipation (LZA) in parallel with the floating-point addition of two operands (A and B) in a computer to significantly reduce the Addition-Normalization time. A combinational network is used to process appropriate XOR (P), AND (G), and NOR (Z) state signals re­sulting from the comparison of the bits in corresponding bit posi­tions of the operands (A and B), starting with the most significant bit (MSB) side of the addition. The state of the initial state signal is detected and shift amount signals are produced and counted for each successive state signal detected, as long as the state remains TRUE. When the state becomes NOT TRUE, adjustments are made depending on the initial state and the successive state, and production of the shift amount signals is halted and an adjustment signal is produced. To determine the exponent of the sum of the floating-point addition, the shift amount count is summed with the adjustment signal. The latter sum will be the exponent of the sum of the operands thus providing a normalized result. The adjustment signal may be based on the CARRY at the NOT TRUE bit position, and the state at the NOT TRUE position may be used to determine whether the result of the addition is positive or negative. In addition to a serial network, an implementing network of a par­allel form which accepts appropriate state inputs as blocks of n bits in length, is disclosed, along with certain special implementation.

公开(公告)号：EP0376266A2

公开(公告)日：1990-07-04

申请号：EP89123982.4

申请日：1989-12-27

申请人： NEC CORPORATION

发明人： Nakamura, Toshihiko

IPC分类号： G06F7/50 ,  G06F5/01

CPC分类号： G06F7/509 ,  G06F5/012 ,  G06F7/485 ,  G06F7/49936

摘要： In a total sum calculation circuit for use in calculating a total sum of first through n-th input data which are represented by a floating point representation and which are composed of first through n-th exponent parts and first through n-th fraction parts, where n is an integer greater than two, an n-input data comparison circuit (32) simultaneously compares the first through the n-th exponent parts with one another to produce a maximum one of the first through the n-th exponent parts and a comparison result signal representative of which one of the first through the n-th exponent parts is the maximum exponent part. Supplied with the first through the n-th exponent parts and the comparison result signal, a shift number calculation circuit (33) calculates first through n-th shift digit numbers between the maximum exponent part and the first through the n-th exponent parts. The first through the n-th fraction parts are shifted by first through n-th shift digit numbers in first through n-th shifters (411-41n) are produced as first through n-th shifted fraction parts which are summed up into an unnormalized fraction part. The unnormalized fraction part is normalized into a total sum fraction part by the use of normalization information derived from the unnormalized fraction part. The maximum exponent part is also normalized by the normalization information into a total sum exponent part. A combination of the total sum exponent part and the total sum fraction part is produced as the total sum represented by the floating point representation.

摘要翻译： 在用于计算至第n输入数据的第一，它们通过浮点表示表示并且的总和使用总和计算电路通过第n指数部分和第一至第n级分部分组成的第一， 其中n是大于二的整数，n输入的数据比较电路（32），同时比较第一至彼此第n个指数部分，以产生第一至第n个指数部分和一个最大的一个一 其中的比较结果信号代表第一至第n个指数部分中的一个是最大指数部分。 与第一至第n个指数部分和比较结果信号供给，移位数计算电路（33），首先计算经过的最大指数部分和第一至第n个指数部分之间的第n移位位数。 第一至第n级分的部分由第一到第n个移位位数通过至第n被制成第一n个移位器（411-41n）移入第一偏移时概括成在非标准化分数份 小数部分。 非标准化分数部分被标准化为通过使用从所述非标准化分数部分衍生归一化信息的总和分数部分。 因此，最大指数部分由归一化信息到总和指数部分归一化。 总和指数部分和总和分数部分的组合被产生作为由浮点表示所表示的总和。

公开(公告)号：EP0233635A3

公开(公告)日：1990-05-09

申请号：EP87102242.2

申请日：1987-02-17

申请人： NEC CORPORATION

发明人： Nukiyama, Tomoji

IPC分类号： G06F5/00

CPC分类号： G06F5/015 ,  G06F5/012

摘要： A shift control circuit comprising an arithmetic circuit (20) for producing a string of a predetermined number of data bits, a logic circuit (22) for detecting the positive or negative sign of the bit string and producing a first switch signal responsive to the positive sign of the bit string or a second switch signal responsive to the negative sign of the bit string, a ones complement generator circuit (24) for producing a signal representative of the ones complement of the bit string, a first selective signal transfer circuit (26) such as a multiplexer which is transparent directly to the bit string in response to the first switch signal or to the signal from the ones complement generator circuit in response to the second switch signal, a decoder circuit (28) for decording the bit string or the signal passed through the first selective signal transfer circuit for producing a decoded output signal, a single-bit shifter circuit (30) for shifting the bit of the decoded output signal by a single bit in a predetermined direction for producing a single-bit shifted output signal, and a second selective signal transfer circuit (32) such as a multiplexer which is transparent directly to the decoded output signal in response to the first switch signal or to the signal from the single-bit shifter circuit (30) in response to the second switch signal.

公开(公告)号：EP0049216A2

公开(公告)日：1982-04-07

申请号：EP81730102.1

申请日：1981-09-30

申请人： Heinrich-Hertz-Institut für Nachrichtentechnik Berlin GmbH

发明人： Talmi, Maati

IPC分类号： G06F5/00

CPC分类号： G06F5/012

摘要： Eine in Rechenanlagen häufig benötigte arithmetische Operation ist das Schieben von Zahlenworten. Die hierzu dienende Rechenwerkeinheit weist gemäß der Erfindung ein Schiebewerkfeld auf, das als dreieckförmige Matrix mit n (n + 1 )/2 Tristate-Elementen in n Spalten und n Zeilen für ein n-stelliges Zahlwort aufgebaut ist und mit dessen Hilfe in einem Schritt mit vom Umfang der Verschiebung unabhängiger, kurzer Dauer das Zahlwort um jede beliebige Anzahl von Stellen verschoben entnommen werden kann.
Mit einem solchen Schiebewerkfeld können auch sowohl Links- als auch Rechtsverschiebungen vorgenommen werden, wenn Ein- und Ausgabeeinheiten vorgesehen sind, die jeweils aus zwei Sätzen zu je n Tristate-Elementen bestehen und das n-stellige Zahlwort jeweils in zueinander spiegelbildlichen Darstellungen aufnehmen.

摘要翻译： 甲在计算机系统中的算术运算经常使用的是数字的推动。 服务为此算术运算单元根据本发明，换档单元字段，其被构造为具有n *（N + 1）中n列/ 2三态元件和n行上的N位数字字的三角矩阵，并且借助于具有在一个步骤的 与独立的，短的持续时间的位移的程度，数目字可以被删除通过任何数量的数字移位。 利用这样的移位单元字段和两个左和右移位，也可以在设置在输入和输出单元，其中每个由两组每个n三态元件，并记录在镜面图像表示在每种情况下的n位数字字制成。

公开(公告)号：EP3040852A1

公开(公告)日：2016-07-06

申请号：EP14200747.5

申请日：2014-12-31

申请人： NXP B.V.

发明人： Barat Quesada, Francisco

IPC分类号： G06F5/01 ,  G06F7/483

CPC分类号： G06F5/012 ,  G06F7/483

摘要： A processor configured to: receive, at a floating-point-input-terminal, an input-block of data comprising a plurality of floating-point numbers (420) each floating-point number (420) comprising a mantissa and an exponent; determine an input-scale-factor (416) based on a previous-input-block-exponent-value associated with a previous-input-block of data; and convert the input-block of data into a fixed-point-block of data (424) in accordance with the input-scale-factor (416), wherein the fixed-point-block of data (424) comprises a plurality of fixed-point-values that can represent the plurality of floating-point numbers within a particular range.

摘要翻译： 一种处理器，被配置为：在浮点输入端接收包括多个浮点数（420）的数据的输入块，每个浮点数（420）包括尾数和指数的每个浮点数（420） 基于与先前输入数据块相关联的先前输入块指数值来确定输入比例因子（416）; 并且根据所述输入比例因子（416）将数据的输入块转换成数据的固定点块（424），其中所述固定点数据块（424）包括多个固定点 可以表示特定范围内的多个浮点数的点值。