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1.发明公开SYSTEM FOR PREVENTING SOFTWARE PIRACY EMPLOYING MULTI-ENCRYPTED KEYS AND SINGLE DECRYPTION CIRCUIT MODULES 失效安排盗版与多个加密的加密及与电路块FOR单个解码防治。
公开(公告)号：EP0238537A1
公开(公告)日：1987-09-30
申请号：EP86905500.0
申请日：1986-08-06
发明人： APPELBAUM, Natthew, Aron , LEHMAN, David, Bruce , NIEGLOS, Donald, Joseph , NOLTE, Stanley, Carl , OEHLER, Michael, Peter
CPC分类号： G06F21/10
摘要： Le système ci-décrit permet l'exécution d'un programme protégé (p. ex. prog. A, prog. B, ...) uniquement par une pluralité sélectionnée d'ordinateurs (p. ex. ordinateur 10) comprenant un code unique respectif Ki pour chaque ordinateur de la pluralité, le code ayant un chiffrement triple (14a) sous la forme EFK ADEKi ADEFK ADKi BD BD BD. Un module respectif (16) est couplé (via 17) à chaque ordinateur (10) de la pluralité d'ordinateurs. Un programme vérificateur (15) dans chaque ordinateur répond à une demande (provenant du poste 11) pour utiliser le programme protégé en effectuant une procédure de déchiffrement unique EFK sur le code à chiffrement triple (étape 22 de la Fig. 2) et envoie le résultat (étape 23) au module (16) sous la forme d'un message. Le module (16) effectue une procédure de déchiffrement unique EKi sur le message (étape 25) et renvoie ce résultat (étape 26) à l'ordinateur. Le programme vérificateur (15) reçoit le résultat du module et effectue une autre procédure de déchiffrement unique EFK sur ce résultat (étape 28) pour obtenir le code Ki. Ensuite, le programme vérificateur (15) utilise le code Ki pour déchiffrer un identificateur, (p. ex. 14b, 14c, ...) et poursuit l'exécution du programme protégé uniquement s'il est identifié par l'identificateur déchiffré (étape 32).
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公开(公告)号：EP0132129A3
公开(公告)日：1987-06-03
申请号：EP84304788
申请日：1984-07-13
IPC分类号： G06F12/10
CPC分类号： G06F12/1027
摘要： An apparatus is disclosed that translates virtual memory addresses into physical memory addresses. In particular, this apparatus comprises a plurality of rows of content addressable memory cells, a corresponding plurality of random access memory cells and another corresponding plurality of control circuits. The content addressable memory cells store the virtual memory addresses and the random access memory cells store the physical memory addresses. The control circuits are coupled to both the content addressable and the random access memory cells and are disposed for controlling the operation of the apparatus.
摘要翻译： 公开了将虚拟存储器地址转换为物理存储器地址的装置。 特别地，该装置包括多行内容可寻址存储器单元，相应的多个随机存取存储单元和另一对应的多个控制电路。 内容可寻址存储器单元存储虚拟存储器地址，并且随机存取存储器单元存储物理存储器地址。 控制电路耦合到内容可寻址存储单元和随机存取存储单元两者，并被设置用于控制设备的操作。
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3.发明公开
公开(公告)号：EP0099262A3
公开(公告)日：1986-11-20
申请号：EP83304007
申请日：1983-07-11
发明人： Potash, Hanan , Green, Howard Hunt
IPC分类号： G06F09/44
CPC分类号： G06F8/447
摘要： Disclosed is a method of transforming an assignment statement of a high level programming language, such as ALGOL and COBOL, into first, second, and third sets of lower level object language instructions wherein instructions of the first set are executable in an interleaved fashion with instructions of the second and third sets, the latter two of which are executable at the same time. When the instructions of the first, second, and third sets are executed in the above-recited fashion, a substantial improvement in the execution time of the corresponding assignment statement is attained.
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公开(公告)号：EP0132361A3
公开(公告)日：1986-04-30
申请号：EP84304846
申请日：1984-07-16
IPC分类号： H02P05/408
CPC分类号： H02P25/024
摘要： A speed control switching circuit for a synchronous motor having windings to which identical switching circuits are coupled. Each switching circuit includes two transistors which are turned on and off alternately to drive current first in one direction through its winding and then in the other direction through its winding. When a transistor is turned off, the current through the winding decreases, and this current drop is sensed, and, at a predetermined dropoff point, the other transistor is turned on.
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5.发明公开Arbitrator circuit and technique for use in a digital computing system having multiple bus controllers 失效用于具有多个总线控制器的数字计算系统中的仲裁器电路和技术
公开(公告)号：EP0122773A3
公开(公告)日：1986-04-23
申请号：EP84302452
申请日：1984-04-11
IPC分类号： G06F03/04
CPC分类号： G06F13/18 , G06F13/364
摘要： In a digital computing system having multiple controllers, multiple memories and multiple memory interfaces, wherein each controller periodically requests access to a memory, an arbitrator device in the memory interfaces is disclosed, which includes circuitry for granting poll requests of the controllers in a prescribed manner of protocol. The arbitrator of this invention includes an input gating structure, a priority encoder, a poll request register and a grant register. During an arbitration cycle, upon reception of one or more active poll signals from the bus controllers, the respective grant signal of the highest priority active poll is immediately returned to the controller. All non-granted poll inputs are disabled so as to lock out any subsequent poll signals. This provides the granted controller exclusive use and control of the data bus between the controller and the memory interface.
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6.发明公开Error-correcting memory with low storage overhead and fast correction mechanism 失效具有低存储和快速校正机制的错误校正存储器
公开(公告)号：EP0077204A3
公开(公告)日：1986-02-12
申请号：EP82305386
申请日：1982-10-11
发明人： Osman, Fazil Ismet
IPC分类号： G06F11/10
CPC分类号： G06F11/1008 , B28D1/041 , F16B2/18 , F16B7/0413 , F16B7/046 , G06F11/1076
摘要： In the disclosed error-correcting memory, data bits are stored in a plurality of memory arrays. Each of said arrays have their memory cells arranged in rows and colums and, a word of said data bits is read by simultaneously selecting one cell at any one row-column pair in every array of said plurality. Every row of each array of said plurality includes a means for storing at least one code bit computed from the data bits in the corresponding row. A plurality of checking means respectively couple to said plurality of arrays for receiving and checking all of the data bits and code bits in the row in its corresponding array from which said one cell is selected to form said word. And an additional memory array means contains memory cells arranged in rows and columns for storing a parity bit at each row-column pair computed from the word of data bits in said plurality of arrays at the corresponding row-column pair.
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公开(公告)号：EP0081820A3
公开(公告)日：1986-01-15
申请号：EP82111435
申请日：1982-12-09
发明人： Bolton, Brent Cecil , Hagenmaier, Card Fredrick, Jr. , Logsdon, Gary Lee , Wilson, Jesse Rudolph
CPC分类号： G06F15/17375 , B61B12/00 , B61B12/007 , G06F13/14 , G06F13/4022 , G06F15/80
摘要： Disclosed is an arbiter switch for use in forming an asynchronous network of concurrent processors where the arbiter switch receives a message from one of two input ports and transmits it to its output port. A path through the network which has been established can be cleared should it become apparent that that particular path has become locked in due to a malfunction of a component in one of the nodes or switches in the network.
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公开(公告)号：EP0109850A3
公开(公告)日：1986-01-08
申请号：EP83307097
申请日：1983-11-21
发明人： Clark, Becky Jane
CPC分类号： H04L49/253 , G06F13/14 , G06F13/4022 , H04L49/254 , H04L49/40
摘要： 57 Disclosed is a selector comprised of one input port and two output ports; the input port has N input data lines and each of the output ports has N output data lines; one circuit in the selector selects only one of the two output ports at a time; and another circuit in the selector passes characters from the input port to the selected output port. Each of the characters is represented by active logic signals on M-out-of-N data lines on the input port, with M being at least two and N being greater than M and greater than three.
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9.发明公开
公开(公告)号：EP0081358A3
公开(公告)日：1985-12-18
申请号：EP82306455
申请日：1982-12-03
发明人： Flora, Laurence Paul
CPC分类号： G06F5/16 , C08L51/04 , C08L71/123 , G06F9/3802 , G06F9/3814 , C08L2666/14 , C08L2666/04
摘要： An execute module in a data processing system is provided with a randomly accessible scratchpad memory which is logically divided into two switchable pages. During operation one page can be written with new instruction data from a fetch module while a previously written page is concurrently being read by the execute module for execution of a designated data processing operation. When the execute module completes execution and requires a new block of data, the two pages are logically switched by toggling an address bit.
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公开(公告)号：EP0142218A3
公开(公告)日：1985-11-27
申请号：EP84305011
申请日：1984-07-24
IPC分类号： B41L01/24
摘要： @ Conditionally self-copying stationery is provided wherein a carbon copy of handwritten material can be made dependently upon the attitude of insertion of a copy sheet (16). The copy sheet (16) has a carbon back coating (54) on one face thereof and each of the writing sheets in a pad (10) has a carbon front coating (52) on the upper surface thereof. Dependently upon whether the copy sheet (16) is inserted such that its carbon back coating (54) makes contact with a carbon front coating (52) or not, so a carbon copy is setectably made or not made. The copy sheet (16) is the conventional writing guide found in writing pads, and is printed on both sides with writing guidelines (26).
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