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公开(公告)号：EP3226058B1
公开(公告)日：2022-03-09
申请号：EP16190250.7
申请日：2016-09-22
发明人： DUVDEVANY, Offir , SHARON, Dadi , SOURANI, Sason
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公开(公告)号：EP3595154A1
公开(公告)日：2020-01-15
申请号：EP19184333.3
申请日：2019-07-04
发明人： GONTHIER, Laurent , LU, Kimi , WANG, Jack
摘要： The disclosure is directed to a power conversion circuit (100) including a bypass circuit (70) for bypassing an inrush current limiting resistor. The power conversion circuit (100) may comprise: a bridge rectifier; at least one current limiting resistor (R ICL ; R1, R2) coupled to the bridge rectifier and an electrical ground (25); at least one controllable current switching device (72; 201, 202) coupled to the current limiting resistor (R ICL ; R1, R2); and at least one driver coupled (74; 74A, 74B) coupled to the current limiting resistor (R ICL ; R1, R2) and the controllable current switching device (72; 201, 202), the at least one driver (74; 74A, 74B) configured to control an operation of the at least one current switching device (72; 201, 202) based on a current or a voltage through the current limiting resistor (R ICL ; R1, R2).
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4.发明公开METHOD FOR CONTROLLING POSITION OF A LINEAR MEMS MIRROR WITH VARIABLE RESOLUTION AND/OR LIGHT INTENSITY 审中-公开用于控制具有可变分辨率和/或光强度的线性MEMS镜片的位置的方法
公开(公告)号：EP3226058A1
公开(公告)日：2017-10-04
申请号：EP16190250.7
申请日：2016-09-22
发明人： DUVDEVANY, Offir , SHARON, Dadi , SOURANI, Sason
CPC分类号： G02B26/0833 , B81B3/0048 , G02B7/1821 , G02B26/0841 , G02B26/105 , G03B21/008
摘要： The method for controlling an angular position of a MEMS mirror includes: applying a first driving moment to the MEMS mirror to generate a rotational scanning movement of the mirror; and, at a zooming instant, applying a second driving moment to the MEMS mirror, wherein the second driving moment is equal to the first driving moment plus an extra moment. The extra moment may be a DC offset. After a transient period of time from zooming instant, a third driving moment M 2 = k θ̇ 2 t is applied. The first and third driving moment are variable linearly with time. The driving moments are applied to torsional springs of the mirror.
摘要翻译： 用于控制MEMS反射镜的角位置的方法包括：向MEMS反射镜施加第一驱动力矩以产生反射镜的旋转扫描运动; 并且在变焦时刻向MEMS反射镜施加第二驱动时刻，其中第二驱动时刻等于第一驱动时刻加上额外时刻。 额外的时刻可能是直流偏移。 在从变焦瞬间过渡一段时间之后，施加第三个驱动时刻M2 =kθ̇2t。 第一和第三驱动时刻随时间线性变化。 驾驶时刻应用于镜子的扭转弹簧。
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公开(公告)号：EP1387498A1
公开(公告)日：2004-02-04
申请号：EP02255421.6
申请日：2002-08-02
摘要： A semiconductor integrated circuit for processing a plurality of received broadcast signals, such as GPS signals, is operable in two modes; acquisition and tracking. In an acquisition mode, a memory arrangement comprising two circulating shift registers circulates samples of a received signal for correlation with a locally generated version of a GPS code. In a tracking mode, the sampled signal is provided direct to the correlators. The same correlators are thereby used to increase acquisition speed.
摘要翻译： 用于处理诸如GPS信号的多个接收的广播信号的半导体集成电路可在两种模式中操作; 采集和跟踪。 在采集模式中，包括两个循环移位寄存器的存储装置循环接收信号的采样，以便与本地生成的GPS码的版本相关。 在跟踪模式中，采样信号被直接提供给相关器。 因此，使用相同的相关器来提高采集速度。
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6.发明公开Method of operating a microcontroller chip having an internal RC oscillator, and microcontroller chip embodying the method 有权一种操作微控制器芯片与内部RC振荡器和微控制器芯片，用于实现该方法的方法
公开(公告)号：EP1378998A1
公开(公告)日：2004-01-07
申请号：EP02291700.9
申请日：2002-07-05
发明人： Shah, Hitesh , Perier, Laurent
IPC分类号： H03L1/00
CPC分类号： H03L1/00
摘要： The chip has a CPU (12), memories (13, 14) for programs and data, peripheral units (18, 19) for interacting with the outside world, and an internal RC oscillator (17) for providing clock signals. One of the peripheral units (18) has a timer counter incremented at a frequency derived from the RC oscillator. The method does not try to change the frequency of the RC oscillator. Instead, an external calibration source (21) is connected to a capture input of the timer unit to provide a signal having a reference frequency, e.g. the mains frequency. The counter is sampled on active edges of that signal, and the sampled values are processed to derive a calibration ratio. After these calibration steps, a software correction is applied to parameters handled by programs stored in memory based on the calibration ratio to compensate for frequency variations of the RC oscillator.
摘要翻译： 该芯片具有用于程序和数据，用于与外界交互的CPU（12），存储器（13,14），外围单元（18，19），以及内部RC振荡器（17），用于提供时钟信号。 一个外围单元（18）的具有在从RC振荡器产生的频率递增一个定时器计数器。 该方法不试图改变RC振荡器的频率。 相反，外部校准源（21）被连接到所述定时器单元的一个捕获输入，以提供具有参考频率的信号，例如 电源频率。 该计数器在信号那样的有源边缘采样，并且将采样值进行处理以导出校准比率。 后合成校准步骤，一个软件校正应用于由存储在基于校准比率存储器以补偿所述RC振荡器的频率变化的程序处理参数。
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公开(公告)号：EP0905610B1
公开(公告)日：2003-11-12
申请号：EP98307887.4
申请日：1998-09-29
发明人： Warren, Robert
IPC分类号： G06F5/06
CPC分类号： G06F5/10
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8.发明公开Compression circuitry for generating an encoded bitstream from a plurality of video frames 审中-公开Komprimierungsanordnung zur Erzeugung eines kodierten Bitstroms aus mehreren Videorahmen
公开(公告)号：EP1347650A1
公开(公告)日：2003-09-24
申请号：EP02251932.6
申请日：2002-03-18
发明人： Bolton, Martin
IPC分类号： H04N7/50
CPC分类号： H04N19/42 , H04N19/126 , H04N19/13 , H04N19/137 , H04N19/15 , H04N19/172 , H04N19/176 , H04N19/61 , H04N19/91
摘要： Compression circuitry for generating an encoded bitstream from a plurality of video frames. Data is DCT transformed and then streamed to a processor where quantised and inverse quantised blocks are generated. A second streaming data connection streams the inverse quantised blocks to an inverse DCT block to generate reconstructed prediction error macroblocks. An addition circuit adds each reconstructed prediction error macroblock and its corresponding predictor macroblock to generate a respective reconstructed macroblock. The quantised macroblocks are zig-zag scanned, run level coded and variable length coded to generate an encoded bitstream.
摘要翻译： 用于从多个视频帧生成编码比特流的压缩电路。 数据被DCT变换，然后流式传输到生成量化和反量化块的处理器。 第二流数据连接将逆量化块流向逆DCT块，以产生重建的预测误差宏块。 加法电路将每个重建的预测误差宏块及其对应的预测器宏块相加以生成相应的重建宏块。 经量化的宏块被锯齿扫描，运行电平编码和可变长度编码以生成编码比特流。
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公开(公告)号：EP1317710A1
公开(公告)日：2003-06-11
申请号：EP01965439.1
申请日：2001-09-11
IPC分类号： G06F12/08 , G11C11/412
CPC分类号： G06F12/0895
摘要： An integrated cache memory circuit is provided comprising a tag RAM, a comparator and a data RAM. Each of the tag RAM and the date RAM have an array of memory cells and plural sense amplifiers. Each memory cell of the RAMs is connected via a respective bit line to one of the plural sense amplifiers. The sense amplifiers of the tag RAM have respective outputs coupled to a first input of the comparator. The comparator having a second input for address information and an output for selectively enabling data output from sense amplifiers of the data RAM. The memory cells of the tag RAM are arranged to have a higher current drive than the memory cells of the data RAM.
摘要翻译： 提供了一种集成高速缓冲存储器电路，其包括标签RAM，比较器和数据RAM。 标签RAM和日期RAM中的每一个具有存储单元阵列和多个读出放大器。 RAM的每个存储单元通过相应的位线连接到多个读出放大器中的一个。 标签RAM的读出放大器具有耦合到比较器的第一输入的相应输出。 该比较器具有用于地址信息的第二输入和用于选择性地启用从数据RAM的读出放大器输出的数据的输出。 标签RAM的存储单元被安排成具有比数据RAM的存储单元更高的电流驱动。
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10.发明公开Circuitry for carrying out square root and division operations 审中-公开Schaltung zurDurchführungvon Quadratwurzel und Divisions operations
公开(公告)号：EP1315080A1
公开(公告)日：2003-05-28
申请号：EP01309851.2
申请日：2001-11-22
发明人： Kurd, Tariq
CPC分类号： G06F7/535 , G06F7/5525
摘要： The invention provides circuitry for carrying out a square root operation and a division operation. The circuitry comprises common iteration circuitry for carrying out a plurality of iterations and means for identifying if an square root operation or a division operation is to be performed. The iteration circuitry is controlled in accordance with whether a square root or division operation is to be performed.
摘要翻译： 本发明提供了用于执行平方根操作和分割操作的电路。 电路包括用于执行多个迭代的公共迭代电路和用于识别是否要执行平方根操作或除法运算的装置。 根据是否执行平方根或除法运算来控制迭代电路。
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