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10 条记录 (耗时 0.01 秒)

    Utilization of unused IO block for core logic functions
    1.
    发明公开
    Utilization of unused IO block for core logic functions 有权
    使用未使用的EA块逻辑核心功能

    公开(公告)号：EP1968193A3

    公开(公告)日：2008-12-17

    申请号：EP08159118.2

    申请日：2003-01-02

    申请人： Sicronic Remote KG, LLC

    发明人： Chauhan, Rajat ,  Kaushik, Rajesh

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17748 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744

    摘要： This invention provides a method and an improved FPGA apparatus for enabling the selective deployment of unused flip-flops or other circuit elements in IO cells and unused decoders or other circuit elements in Look Up Tables (LUT), for core logic functions, comprising disconnecting means for selectively disconnecting unused circuit elements from the IO pad circuitry or from said LUT circuitry, and connecting means for selectively connecting said disconnected circuit elements either to the connection matrix of the core logic or between themselves to provide independently configured functions.

    Method and apparatus of reloading erroneous configuration data frames during configuration of PLDs
    8.
    发明公开
    Method and apparatus of reloading erroneous configuration data frames during configuration of PLDs 审中-公开
    可编程逻辑器件的配置过程中的方法和用于不正确的配置数据的装置herladen

    公开(公告)号：EP1411431A3

    公开(公告)日：2010-10-20

    申请号：EP03020154.5

    申请日：2003-09-05

    申请人： Sicronic Remote KG, LLC

    发明人： Goel, Ashish Kumar ,  Khanna, Namerita ,  Aggarwal, Davinder

    IPC分类号： G06F11/14 ,  G06F17/50

    CPC分类号： G06F11/1402 ,  G01R31/318519 ,  G06F11/1008

    摘要： The invention provides an improved method and apparatus for reloading only those frames in which errors are detected during the FPGA configuration. A configuration data frame for a FPGA is sumultaneously loaded to the Frame register of the FPGA and also to an error detection circuit which detects errors with the loaded frame. An error counter value is maintained by the apparatus and is incremented each time an error with a frame is detected. The incremented value is compared by a Comparator circuit with a pre-determined threshold value 'n'. If a match is found then the configuration process is aborted, else the data frame is reloaded in the configuration memory, transferred again to the frame register and recheked for errors. If no error os detected with the reloaded frame, the error counter value is reset and the next frame is loaded until the FPGA configuration process is over.

    A field programmable device
    9.
    发明公开
    A field programmable device 有权
    现场可编程设备

    公开(公告)号：EP2051381A1

    公开(公告)日：2009-04-22

    申请号：EP08022536.0

    申请日：2002-04-03

    申请人： Sicronic Remote KG, LLC

    发明人： Deepak, Agarwal

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17748 ,  H03K19/17704 ,  H03K19/17736

    摘要： A field programmable device comprising: a plurality of logic blocks; a plurality of lines extending at least partially through said device; a plurality of configurable connections connected to the logic blocks, and comprising switch matrices, the switch matrices comprising: switching means comprising at least one multiplexer; and configurable latches; whereby in a configuration mode, the switching means causes configuration signals to be passed to at least one of said configurable latches via said plurality of lines for storing said configuration signals, and in a processing mode, said plurality of lines are used to carry data to at least one logic block.

    摘要翻译： 一种现场可编程设备，包括：多个逻辑块; 多条线，其至少部分地延伸穿过所述装置; 连接到逻辑块并包括开关矩阵的多个可配置连接，开关矩阵包括：包括至少一个多路复用器的开关装置; 和可配置的锁存器; 由此在配置模式中，所述切换装置使配置信号经由所述多条线路传递到所述可配置锁存器中的至少一个，用于存储所述配置信号，并且在处理模式中，所述多条线路用于将数据传送到 至少一个逻辑块。

    Utilization of unused IO block for core logic functions
    10.
    发明公开
    Utilization of unused IO block for core logic functions 有权
    未使用的IO模块用于核心逻辑功能

    公开(公告)号：EP1968193A2

    公开(公告)日：2008-09-10

    申请号：EP08159118.2

    申请日：2003-01-02

    申请人： Sicronic Remote KG, LLC

    发明人： Chauhan, Rajat ,  Kaushik, Rajesh

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17748 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744

    摘要： This invention provides a method and an improved FPGA apparatus for enabling the selective deployment of unused flip-flops or other circuit elements in IO cells and unused decoders or other circuit elements in Look Up Tables (LUT), for core logic functions, comprising disconnecting means for selectively disconnecting unused circuit elements from the IO pad circuitry or from said LUT circuitry, and connecting means for selectively connecting said disconnected circuit elements either to the connection matrix of the core logic or between themselves to provide independently configured functions.

    摘要翻译： 本发明提供了一种方法和一种改进的FPGA装置，用于实现IO单元中未使用的触发器或其他电路元件和查找表（LUT）中的未使用解码器或其他电路元件的选择性部署，用于核心逻辑功能，包括断开装置 用于选择性地从IO垫电路或从所述LUT电路中断开未使用的电路元件，以及连接装置，用于选择性地将所述断开的电路元件连接到核心逻辑的连接矩阵或其间以提供独立配置的功能。