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    CMOS IMAGE SENSOR WITH PIXEL LEVEL GAIN CONTROL
    2.
    发明授权
    CMOS IMAGE SENSOR WITH PIXEL LEVEL GAIN CONTROL 有权
    与像素级的增益控制CMOS图像传感器

    公开(公告)号：EP1151601B1

    公开(公告)日：2004-07-14

    申请号：EP99964195.4

    申请日：1999-12-09

    申请人： Agilent Technologies, Inc.

    发明人： FOWLER, Boyd

    IPC分类号： H04N3/15

    CPC分类号： H04N5/378 ,  H04N5/3742

    摘要： An image sensor and method of sensing an image provides a variable amplifier at each pixel, thereby expanding the dynamic range of the sensor. An image sensor core (500) comprises a plurality of pixel sensors (510). Each pixel sensor preferably includes a photosensitive element (310), a variable amplifier (312), and an analog-to-digital converter ("ADC") (314). The ADC (512) includes a comparator (512) coupled to a latch/shift register (514). The comparator (512) receives the output of the variable amplifier (312) and a ramp signal and produces an output when the ramp signal exceeds the amplifier (312) output. The latch/shift register (514) latches a count signal corresponding to the ramp signal when triggered by the comparator (512). In operation, the photosensitive element (310) is exposed to light for a first integration period. The variable amplifier (312) amplifies the resulting photocharge by the maximum possible amount. The ADC (314) converts the photocurrent to a digital signal and latches the five most significant bits in memory (514). These five bits are provided in parallel to the variable amplifier (312) to set the amplification level. Then, the photosensitive element (310) is exposed to light for a second integration period and the resulting photocharge is amplified at the set amplification level. The output of the amplifier (312) is digitized by the ADC (314) and the latch/shift register (514) stores the 12-bit result. The five bits selecting the amplification level and the 12-bit result provide the image sensor with 17 bits of dynamic range.

    Multi tone decoder system
    4.
    发明公开
    Multi tone decoder system 失效
    多音频解码器系统

    公开(公告)号：EP1202516A3

    公开(公告)日：2003-01-02

    申请号：EP01128019.5

    申请日：1996-03-08

    申请人： NATIONAL SEMICONDUCTOR CORPORATION

    发明人： Greiss, Israel ,  Drucker, Rami ,  Montag, Gil ,  Shabtay, Ophir ,  Almagor, David

    IPC分类号： H04L27/26 ,  H04B3/23 ,  H04B3/21

    CPC分类号： H04L27/30 ,  H04B3/23 ,  H04L5/143 ,  H04L5/1461

    摘要： Near-end echo-reduction is achieved by passing a transmit signal through a first filter bank and feeding a remote signal plus an echo of the transmit signal through a second filter bank, then subtracting a gain-coefficient-compensated (scaled) version of the filtered transmit signal from the filtered-composite-remote signal to obtain an echo-reduced receive signal. The echo-reduced receive signal is suitably employed by tone decoders, voice response mechanisms, and the like, in a telephone system, and avoids false alarms due to near-end echo. In one embodiment, the gain coefficients are fixed for each frequency of interest. In another embodiment, the gain coefficients are dynamically arrived at based on the filtered transmit signal and the echo-reduced receive signal. The two filter banks can be combined in one, multiplexed filter bank.

    摘要翻译： 通过使发送信号通过第一滤波器组并通过第二滤波器组馈送远程信号加上发送信号的回声，然后减去增益系数补偿（缩放）版本的 从经过滤波的复合远程信号中滤波后的发射信号以获得回波减小的接收信号。 回声降低后的接收信号适用于电话系统中的音调解码器，语音响应机制等，并且避免了由于近端回声引起的错误警报。 在一个实施例中，增益系数针对每个感兴趣的频率是固定的。 在另一个实施例中，基于经滤波的发射信号和回声降低的接收信号动态地获得增益系数。 两个滤波器组可以组合在一个多路复用滤波器组中。

    EEPROM memory cell
    5.
    发明授权
    EEPROM memory cell 失效
    EEPROM存储单元

    公开(公告)号：EP0699344B1

    公开(公告)日：2002-09-25

    申请号：EP95908541.6

    申请日：1995-01-20

    申请人： NATIONAL SEMICONDUCTOR CORPORATION

    发明人： MANLEY, Martin, H.

    IPC分类号： H01L29/788 ,  H01L27/115 ,  H01L21/336 ,  H01L21/8247

    CPC分类号： H01L27/115 ,  H01L29/7883

    摘要： A method of semiconductor fabrication, in which a single aperture is used to define both a thin oxide tunneling region and a drain diffusion region in a self-aligned fashion, produces a device structure suitable for use in an electrically-erasable read-only memory (EEPROM) cell. A gate oxide is grown, then a photoresist mask is formed having a slit for ion implantation into the drain diffusion region. The oxide within the slit is etched away, and ion implantations forms a drain diffusion region. After the mask is stripped away, a healing furnace cycle removes the implant damage. A thin tunnel oxide layer is grown over the drain diffusion region, and then a polysilicon floating gate is formed so that one edge of this gate intersects a portion of the area of tunnel oxidation so as to form a small region of tunnel oxide under the floating gate. The process sequence then reverts to a conventional MOS flow. The self-aligned drain diffusion region and tunnel oxide region can be used in a variety of EEPROM cell designs. One embodiment involves a double-polysilicon, single-metal process in which thre diffusion regions are used to form the EEPROM cell. The second layer of polysilicon overlies the floating gate and forms a control gate word line. The control gate and the floating gate overly the channel between the drain diffusion region and a common source diffusion region. The first layer of polysilicon is also used to form a select gate overlying the channel between the drain diffusion region and a select drain diffusion region. The metal layer provides contact to the select drain diffusion region and forms the bit line.

    Method of fabricating an electrically programmable read-only memory
    9.
    发明授权
    Method of fabricating an electrically programmable read-only memory 失效
    一种用于制造电可编程只读存储器的过程

    公开(公告)号：EP0698295B1

    公开(公告)日：2002-05-29

    申请号：EP95908063.1

    申请日：1995-01-20

    申请人： NATIONAL SEMICONDUCTOR CORPORATION

    发明人： BERGEMONT, Albert ,  WOLSTENHOLME, Graham, R.

    IPC分类号： H01L27/115 ,  H01L21/8247

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

    摘要： The bit lines in an alternate-metal, virtual-ground (AMG) electrically programmable read-only-memory (EPROM), are formed by utilizing a plurality of field oxide regions and a plurality of pairs of dielectric/floating gate strips, which have the ends of each pair of strips connected together over a field oxide region, as an implant mask. By connecting together the ends of each pair of dielectric/floating gate strips, the width of the strips at the edges of the field oxide regions will remain constant. As a result, the isolation between adjacent bit lines, which is defined by the width of the strips, will also remain constant.

    METHOD OF FORMING A MOULDED LEAD FRAME
    10.
    发明授权
    METHOD OF FORMING A MOULDED LEAD FRAME 失效
    VERFAHREN ZUR HERSTELLUNG EINES VERGOSSENEN LEITERRAHMENS

    公开(公告)号：EP0698292B1

    公开(公告)日：2001-12-05

    申请号：EP95910108.0

    申请日：1995-01-20

    申请人： NATIONAL SEMICONDUCTOR CORPORATION

    发明人： PRUITT, David, A.

    IPC分类号： H01L23/495 ,  H01L21/48

    CPC分类号： H01L21/4821 ,  H01L23/49568 ,  H01L23/49579 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A lead frame (32) for use in an integrated circuit package (30) is herein disclosed wherein the lead frame is produced by molding an electrically conductive material into a desired lead frame shape. There is also disclosed several possible arrangements for a lead frame (32) produced using the molding method including protrusions (36) on the lead frame (32) adapted to provide a mechanical connection to the integrated circuit package (30), a heat sink (38) molded as an integral part of the lead frame (32) with heat dissipating characteristics specific to the application in which the lead frame (32) will be used, and an arrangement which provides a heat conducting portion adapted to thermally connect a component attached to the lead frame (32) to an external heat sink.

    摘要翻译： 本文公开了一种用于集成电路封装的引线框架，其中引线框架通过将导电材料模制成所需的引线框架形状来制造。 还公开了使用模制方法制造的引线框架的几种可能的布置，包括引线框架上的凸起，适于提供与集成电路封装件的机械连接，散热器作为引线框架的整体部分模制，散热 特征于使用引线框架的应用的特征，以及提供适于将附接到引线框架的部件热连接到外部散热器的导热部分的布置。