Abstract:
An integrated circuit comprises a threshold generation circuitry for generating at least one differential voltage signal. The threshold generation circuitry comprises at least one common mode current generation circuit arranged to generate at least one common mode current signal, whereby said at least one common mode current signal is combined with at least one input current signal to produce a combined current signal comprising a combined signal common mode component. Conversion circuitry is arranged to receive the combined current signal and convert the combined current signal into the at least one differential voltage signal for use within the comparator circuit. The threshold generation circuitry further comprises feedback circuitry arranged to receive an indication of the combined signal common mode component, compare the received indication to a reference value, and regulate the at least one common mode current signal based at least partly on the comparison results.
Abstract:
A wireless communication unit includes a transmitter, a receiver, a selectivity element and a baseband processing module. The receiver has at least one summation module arranged to add a cancellation signal to the quadrature baseband receive signal. a baseband processing module arranged to: receive the quadrature baseband transmit signal and quadrature baseband receive signal; apply independent gain and phase adjustments to quadrature portions of the quadrature baseband transmit signal, based on at least one signal component of the quadrature baseband receive signal, to form independent cancellation signals; and apply the independent cancellation signals to the at least one summation module.
Abstract:
A network element for controlling a usage of at least one resource is described. The network element comprises: a transmitter for transmitting a signal identifying at least one uplink resource to at least one wireless communication unit; a signal processor operably coupled to the transmitter for generating the signal; and a receiver for receiving a transmission from the at least one wireless communication unit on the identified at least one uplink resource. The signal processor is arranged to allocate the uplink resource for the at least one wireless communication unit in a first portion of a first sub-frame on a first frequency and a first portion of a second sub-frame on a second frequency wherein a time gap is allocated between an end of the first portion of the first sub-frame and a beginning of the first portion of a second sub-frame.
Abstract:
An integrated circuit is described for providing a power supply to a radio frequency (RF) power amplifier (PA). The integrated circuit comprises a low-frequency power supply path comprising a switching regulator and a high-frequency power supply path arranged to regulate an output voltage of a combined power supply at an output port of the integrated circuit for coupling to a load. The high- frequency power supply path comprises: an amplifier comprising a voltage feedback and arranged to drive a power supply signal on the high-frequency power supply path; and a high-frequency-path supply module arranged to provide a high frequency supply to drive the amplifier, where the high-frequency-path supply module comprises a pulse-width modulator operably coupled to the high frequency supply via a filter and arranged to provide a filtered pulse-width modulated signal to the high frequency supply.
Abstract:
A radio frequency integrated circuit (635) for a wireless device (500) to an antenna (502), wherein the antenna (502) is coupled to the radio frequency circuit (602) via at least one off-chip inductor (611, 613) that forms a first portion of an antenna matching circuit (530), wherein the integrated circuit (635) includes: a first port coupleable to the radio frequency integrated circuit (635); a second port coupleable to the antenna (502), and a second portion of the antenna matching circuit (530) located between the first port and second port and coupled in parallel with the at least one off-chip inductor (611, 613). The second portion of the antenna matching circuit (530) includes: at least one on-chip inductor (615, 617); and at least one radio frequency switch (606, 616) coupled in series with the at least one on-chip inductor (615, 617) and arranged to selectively introduce the at least one on-chip inductor (615, 617) into the antenna matching circuit (530).