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1.发明公开
公开(公告)号：EP1870752A1
公开(公告)日：2007-12-26
申请号：EP07011993.8
申请日：2007-06-19
发明人： Lee, Birk
摘要： An optical receiver is provided, which includes a housing, an objective lens (120) situated in the housing, a solid immersion lens (SIL) (126; 226; 326; 426; 526; 626) mounted onto the housing, and thermal management element affixed to the housing to control the temperature of the SIL. The thermal management apparatus or element may be a coolant conduit (214; 3145; 414; 514; 614), a thermoelectric cooling (TEC) device (316; 416; 516), etc. A coolant spray may also be provided to spray the imaged specimen.
摘要翻译： 提供了一种光接收器，其包括壳体，位于壳体中的物镜（120），安装在壳体上的固体浸没透镜（SIL）（126; 226; 326; 426; 526; 626）和热管理 元件固定在壳体上以控制SIL的温度。 热管理装置或元件可以是冷却剂管道（214; 3145; 414; 514; 614），热电冷却（TEC）装置（316; 416; 516）等。还可以提供冷却剂喷雾器以喷射 成像标本。
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公开(公告)号：EP0868687B1
公开(公告)日：2006-06-07
申请号：EP96942804.4
申请日：1996-11-21
CPC分类号： G01R31/2851 , G01R31/31813 , G01R31/31907 , G01R31/3191 , G01R31/31921 , G01R31/31922 , G06F1/025 , G06F1/04
摘要： A timing signal generator includes a voltage controlled oscillator (VCO), a logic circuit, N set circuits and N reset circuits and a bistable latch circuit. The VCO produces a set of N reference signals frequency locked to a reference clock signal and distributed in phase so as to evenly resolve the reference clock period into N intervals. The logic circuit asserts ones of N set signals and N reset signals selected by input control words. Each set circuit receives one of the N set signals and one of the N reference signals and briefly couples an output node to high logic level source in response to a leading edge of the received reference signal when its received set signal is asserted. Each reset circuit receives one of the N reset signals and one of the N reference signals and briefly couples the output node to low logic level source in response to a leading edge of its received reference signal when it reset signal is asserted. The bistable circuit maintains the output node at its current logic level after the output node is decoupled from either of the sources. The timing of leading and trailing edges of pulses of the output timing signal may be controlled with a resolution that is 1/Nth of the period of the reference clock by supplying an appropriate control word sequence to the logic circuit.
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3.发明授权
公开(公告)号：EP0990165B1
公开(公告)日：2004-09-22
申请号：EP98918741.4
申请日：1998-04-27
IPC分类号： G01R31/28 , G01R31/3183 , G06F13/16
CPC分类号： G01R31/31908 , G01R31/31921
摘要： An integrated circuit tester includes a node for each terminal of a device under test. Each node includes a pin electronics circuit for carrying out test activities at the device terminal and a vector memory system for supplying a vector sequence to the local pin electronics circuit for controlling its test activities. To program the tester, a host computer transmits an appropriate set of vectors to each vector memory system via a common bus. Before sending vectors to the vector memory systems, the host computer sends them control data assigning each to one or more "virtual channels" such that all vector memory systems that are to receive a similar set of vectors are assigned to a similar virtual channel. Also, before transmitting each set of vectors on the bus, the host computer broadcasts additional control data to all vector memory systems designating one virtual channel as active. Thereafter only those vector memory systems assigned to the active virtual channel accept the transmitted vector set. Thus the host computer can concurrently write the same set of vectors to more than one vector memory system when the pin electronics circuits they control are to carry out similar test activities.
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公开(公告)号：EP0979389B1
公开(公告)日：2004-07-07
申请号：EP98920138.9
申请日：1998-04-30
发明人： KHATER, Nabil , BAKER, David, A.
IPC分类号： G01D21/00
CPC分类号： G01R31/2887
摘要： A cable tray assembly for a manipulator (200) within a testing device (100). A manipulator including cables is used for manipulating a testing head (62) for testing semiconductor devices. The cable trays (102) of the present invention are mounted within the manipulator within a cable housing (26) and are mounted on respective rails (16) allowing them to move longitudinally in and out with respect to the cable housing. The cable trays receive and support cables that run from a frame (2) of a tester system to the testing head. As the manipulator is moved to position the testing head, this causes the cables to move. In response, the cable trays independently move with the movement of the cables so as to allow for a full range of motion of the manipulator while simultaneously relieving compression and tension within the cables which reduces long term cable damage. The cable trays have a greater height with respect to their width so that the cables can more readily flex about an axis parallel to the cable tray height. The cable trays also contain a contoured flange at the bottom of each cable tray to prevent cable chafing. Further, the ends of the cable trays are tapered in length at different angles to maximize cable support while reducing cable tension during flexing.
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公开(公告)号：EP1249026A1
公开(公告)日：2002-10-16
申请号：EP01942786.3
申请日：2001-01-16
CPC分类号： H01H51/28 , G01R31/3004 , G01R31/31926 , G01R31/3193 , H01H49/00 , H01H50/10 , H01H50/44 , H01H51/281
摘要： A relay (70) includes contacts (73) residing within a glass tube (72). A coil (76) surrounding the tube (72) and a switch (66) are connected in parallel between two terminals (77) of the relay (70). A current source supplies a current to the coil (76) and switch (66). When the switch (66) is open, substantially all of the current passes through the coil (76) and the coil (76) produces a sufficient amount of magnetic flux to close the relay's contacts (73). When the switch (66) closes, it shunts a sufficient amount of the current away from the coil (76) to reduce the magnetic flux it produces below the level needed to keep the contacts (73) closed. The current source is sized so that the coil (76) requires relatively few turns, thereby allowing the relay (70) to be relatively thin. The coil (76) is formed by a conductor (140) embedded in an insulating substrate (128) surrounding the tube (72).
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6.发明公开INSTRUCTION PROCESSING PATTERN GENERATOR CONTROLLING AN INTEGRATED CIRCUIT TESTER 审中-公开订单处理SANTANDER图形发生器其中TEST DRIVE集成电路CONTROLS
公开(公告)号：EP1129363A1
公开(公告)日：2001-09-05
申请号：EP99956557.5
申请日：1999-10-25
IPC分类号： G01R31/28
CPC分类号： G01R31/318371 , G01R31/31921
摘要： A pattern generator (23) for an integrated circuit tester includes an instruction memory (22) storing addressable instructions (INST) and reading out each instruction when addressed by an address (ADDR) supplied as input thereto. An instruction processor (20) receives each instruction read out of the instruction memory (22) and alters the address input to the instruction memory (22) in accordance with the received instruction so that the instruction memory (22) reads out a next instruction. The instruction processor (20), which includes a conventional return address stack, is capable of executing conventional address increment, call and return instructions. The instruction processor (20) is also capable of executing a temporary return instruction (TEMP) by incrementing its current address output to produce a new return address, by setting its address output to the value of a return address previously saved in the stack, by popping the saved return address from the stack, and by pushing the new return address onto the stack. Temporary return instructions enable instruction program flow to pass back and forth between a main program and a called subroutine.
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公开(公告)号：EP1125140A1
公开(公告)日：2001-08-22
申请号：EP99971094.0
申请日：1999-10-25
发明人： WASSON, Will
IPC分类号： G01R31/28
CPC分类号： G01R31/31921 , G01R31/31908
摘要： An integrated circuit (IC) tester includes set of tester channels, each for carrying out a test activity at a separate terminal of an IC device under test (DUT) during each cycle of a test. The tester also includes a disk drive having a removable disk for reading out scan or programming data to the tester channels during a test. Each tester channel includes an instruction memory for storing a set of instructions, and each tester channel executes its stored instructions during the test. Some of the instructions include VECTOR data directly indicating a particular test activity the tester channel is to carry out at a DUT terminal during a next test cycle. Others of the instructions tell the tester channel to acquire a particular number (N) of serial data bits as they are read out of the disk drive and to carry out an activity during each of the next N test cycles indicated by a state of a corresponding one of the N serial data bits.
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公开(公告)号：EP1095287A1
公开(公告)日：2001-05-02
申请号：EP99927320.4
申请日：1999-06-07
IPC分类号： G01R31/28
CPC分类号： G01R31/31935 , G01R31/316
摘要： A general purpose integrated circuit (I) tester (10) includes a set of channels (18), one for each input or output pin of an I device under test (DUT) (12). Each channel (18) is programmed by a host computer (22) to either supply a test signal to a DUT I/O pin (14, 16) or sample a DUT output signal appearing at the I/O pin (14, 16) and produce sample data representing its magnitude or logic state. The tester (10) also includes an amorphous logic circuit (ALC) (30) having a set of input and output terminals (28) and a programmable logic circuit interconnecting the input and output terminals. Some of the ALC input and output terminals (28) receive the sample data produced by each channel (18) and other ALC terminals send control signals directly to each channel (18). Other ALC terminals transmit data to the host computer (22).
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公开(公告)号：EP1051805A1
公开(公告)日：2000-11-15
申请号：EP99904263.3
申请日：1999-01-26
发明人： LESMEISTER, Gary, J.
摘要： A self-calibrating programmable phase shifter (50) includes a tapped delay line (52) for successively delaying a periodic reference signal to produce a set of phase distributed tap signals. A multiplexer (54) selects one of the tap signals as input to a programmable delay circuit (56) which further delays the selected tap signal to produce an output signal that is phase shifted from the reference signal. A conversion table (58) converts input data indicating a desired phase shift between the reference signal and the output signal into output data for controlling the multiplexer selection and the amount of delay provided by the programmable delay circuit. The phase shifter includes calibration circuitry (60, 84) that converts the phase shifter into an oscillator by feeding the output signal back as input to the tapped delay line and adjusting relationships between the conversion table input and output data so that the period of the output signal has a desired linear relationship to the input data value.
摘要翻译： 自校准可编程移相器（50）包括用于连续地延迟周期性参考信号以产生一组相位分布抽头信号的抽头延迟线（52）。 多路复用器（54）选择抽头信号之一作为输入到可编程延迟电路（56）的输入，该可编程延迟电路进一步延迟所选抽头信号以产生与参考信号相移的输出信号。 转换表（58）将表示参考信号和输出信号之间的期望相移的输入数据转换成用于控制多路复用器选择的输出数据和由可编程延迟电路提供的延迟量。 移相器包括校准电路（60,84），其通过将输出信号作为输入反馈到抽头延迟线并且调整转换表输入和输出数据之间的关系以将输出的周期 信号与输入数据值具有期望的线性关系。
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10.发明公开MODULAR INTEGRATED CIRCUIT TESTER WITH DISTRIBUTED SYNCHRONIZATION AND CONTROL 审中-公开模块化的测试设备与分布式同步和控制集成电路的
公开(公告)号：EP1032844A1
公开(公告)日：2000-09-06
申请号：EP98955133.8
申请日：1998-10-26
IPC分类号： G01R31/26
CPC分类号： G01R31/31908 , G01R31/31907 , G01R31/31922
摘要： A modular integrated circuit tester (10) includes a set of tester modules (14) for carrying out a sequence of tests on an integrated circuit device under test (DUT) (12). Each module includes a memory (54) for storing instruction sets indicating how the module is to be confugured for each test of the sequence. Before the start of each test, a microcontroller (30) in each module executes an instruction set to appropriately configure the module for the test. The microcontroller in each module thereafter sends a ready signal to a start logic circuit (20) in each other module indicating that it is ready to perform the test. When microcontroller of all modules taking part in the test have signaled they are ready, the start logic circuit in each module signals its microcontroller to begin the test. The molules then carry out the test with their activities synchronized to a master clock signal. The process of configuring the modules, generating the ready signals and commencing a test is repeated for each test of the sequence.
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