INTEGRATED CIRCUIT TESTER WITH AMORPHOUS LOGIC
    1.
    发明公开
    INTEGRATED CIRCUIT TESTER WITH AMORPHOUS LOGIC 审中-公开
    无定形LOGIC ICT测试仪

    公开(公告)号:EP1095287A4

    公开(公告)日:2004-12-29

    申请号:EP99927320

    申请日:1999-06-07

    CPC分类号: G01R31/31935 G01R31/316

    摘要: A general purpose integrated circuit (I) tester (10) includes a set of channels (18), one for each input or output pin of an I device under test (DUT) (12). Each channel (18) is programmed by a host computer (22) to either supply a test signal to a DUT I/O pin (14, 16) or sample a DUT output signal appearing at the I/O pin (14, 16) and produce sample data representing its magnitude or logic state. The tester (10) also includes an amorphous logic circuit (ALC) (30) having a set of input and output terminals (28) and a programmable logic circuit interconnecting the input and output terminals. Some of the ALC input and output terminals (28) receive the sample data produced by each channel (18) and other ALC terminals send control signals directly to each channel (18). Other ALC terminals transmit data to the host computer (22).

    Apparatus for heating electronic components
    2.
    发明公开
    Apparatus for heating electronic components 审中-公开
    Vorrichtung zum Aufheizen von elektronischen Komponenten

    公开(公告)号:EP1037062A3

    公开(公告)日:2004-01-07

    申请号:EP00301787.8

    申请日:2000-03-03

    IPC分类号: G01R31/28

    CPC分类号: G01R31/316

    摘要: A test fixture for the testing of electronic assemblies (6). The test fixture including locating means to allow the electronic assembly or assemblies (6) placed therein to be located in the required test locations. The fixture also includes at least one heating means (2) which is located with respect to the electronic assemblies (6) to contact with one or a plurality of the components which are required to be heated during the testing of the electronic assembly (6).

    摘要翻译: 用于电子组件测试的测试夹具(6)。 测试夹具包括定位装置,以允许放置在其中的电子组件或组件(6)位于所需的测试位置。 固定装置还包括至少一个相对于电子组件(6)定位的加热装置(2),以在电子组件(6)的测试期间与需要加热的一个或多个部件接触, 。

    Circuit and method for trimming integrated circuits
    3.
    发明公开
    Circuit and method for trimming integrated circuits 有权
    电路和方法,用于修整集成电路

    公开(公告)号:EP1126524A3

    公开(公告)日:2003-10-15

    申请号:EP01400157.2

    申请日:2001-01-19

    发明人: SHYR, You-Yuh

    IPC分类号: H03M1/10 H01L27/02

    摘要: A programmable after-package, on-chip reference voltage trim circuit for an integrated circuit having a plurality of programmable trim cells generating a programmed sequence. A converter is provided to convert the bit sequence into a trim current. The trim current is added to an initial value of a reference voltage to be trimmed, as generated by the integrated circuit. Once the correct value of the trim current is determined, isolation circuitry is programmed to isolate the trim circuitry from the remainder of the IC, thereby freeing the logic and package pins associated with the IC for use by users of the IC. The preferred trim circuitry includes fuses which are blown in accordance with a bit value supplied to the trim cell to permanently fix a trim current value, once a best fit value is determined.

    Multiplexing electronic test probe
    5.
    发明公开
    Multiplexing electronic test probe 失效
    电子测试探针与复用

    公开(公告)号:EP0721109A3

    公开(公告)日:1997-07-16

    申请号:EP95116737.8

    申请日:1995-10-24

    IPC分类号: G01R1/073

    摘要: An analog electronic test probe (100) includes hundreds of inputs (105), each connected to two amplifiers (1130), each in a separate multiplexer stage (890, 891) on an integrated circuit (802). A programmer (121), responsive to a dial (145), shifts data through a shift register (1190) of latches, each of which is connected to one of the amplifiers (1130), activating the amplifier(s) connected to the selected input (105), thereby multiplexing it (them) to selected output(s) (129, 130). Similarly, the gain for each output may be selected. An outdisable circuit (100) connected to the outputs (871, 873, 874) of each multiplexer (810, 811, 812) and the outputs (872, 876) of each IC chip (802) causes each output to appear electrically as an open circuit when no input (105) associated with the multiplexer (810) or chip (802) is selected. This permits any number of multiplexers (810) and IC chips (802) to be daisy-chained together.

    Multiplexing electronic test probe
    6.
    发明公开
    Multiplexing electronic test probe 失效
    ElektronischerTestfühlermit Multiplexing

    公开(公告)号:EP0721109A2

    公开(公告)日:1996-07-10

    申请号:EP95116737.8

    申请日:1995-10-24

    IPC分类号: G01R1/073

    摘要: An analog electronic test probe (100) includes hundreds of inputs (105), each connected to two amplifiers (1130), each in a separate multiplexer stage (890, 891) on an integrated circuit (802). A programmer (121), responsive to a dial (145), shifts data through a shift register (1190) of latches, each of which is connected to one of the amplifiers (1130), activating the amplifier(s) connected to the selected input (105), thereby multiplexing it (them) to selected output(s) (129, 130). Similarly, the gain for each output may be selected. An outdisable circuit (100) connected to the outputs (871, 873, 874) of each multiplexer (810, 811, 812) and the outputs (872, 876) of each IC chip (802) causes each output to appear electrically as an open circuit when no input (105) associated with the multiplexer (810) or chip (802) is selected. This permits any number of multiplexers (810) and IC chips (802) to be daisy-chained together.

    摘要翻译: 模拟电子测试探针(100)包括数百个输入(105),每个输入(105)连接到两个放大器(1130),每个放大器在集成电路(802)上的单独的多路复用器级(890,891)中。 响应于拨号盘(145)的编程器(121)通过锁存器的移位寄存器(1190)移位数据,每个锁存器连接到放大器(1130)中的一个,激活连接到所选择的放大器 输入(105),从而将它们(它们)复用到选择的输出(129,130​​)。 类似地,可以选择每个输出的增益。 连接到每个多路复用器(810,811,812)的输出(871,873,874)和每个IC芯片(802)的输出(872,876)的不稳定电路(100)使得每个输出以电 当没有选择与多路复用器(810)或芯片(802)相关联的输入(105)时,开路。 这允许任何数量的多路复用器(810)和IC芯片(802)被菊花链连接在一起。

    Prescaler IC test method capable of executing alternate current test by the use of IC tester for direct current test
    7.
    发明公开
    Prescaler IC test method capable of executing alternate current test by the use of IC tester for direct current test 失效
    对于predisector IC测试的方法,所述AC测试可以通过集成电路测试仪DC测试运行

    公开(公告)号:EP0702303A1

    公开(公告)日:1996-03-20

    申请号:EP95113726.4

    申请日:1995-08-31

    申请人: NEC CORPORATION

    发明人: Takano, Isamu

    摘要: In a prescaler IC test method for carrying out a characterization test to decide whether or not a prescaler IC is normal by the use of an IC tester for carrying out a predetermined decision operation and a probe card for mounting said prescaler IC kept on a wafer, the prescaler IC carries out a frequency dividing operation on reception of a frequency signal to produce a frequency divided signal. The characterization test comprises the steps of generating the frequency signal to supply the frequency signal to the prescaler IC on reception of a direct current control signal, converting the frequency divided signal into a converted signal having a predetermined signal width and a signal level, detecting a first mean value of the signal level, and supplying the first mean value to the IC tester in the form of a direct current signal. The IC tester is supplied with the first mean value and carries out the predetermined decision operation by the use of the first mean value.

    摘要翻译: 在用于进行表征测试,以决定IC是否一个分频器是正常通过使用IC测试器的用于执行一个预定的判决操作和探针板,用于安装所述预分频器IC的预分频器IC测试方法保持在晶片上, 预分频器IC执行分频操作上的频率信号,以产生分频信号的接收。 表征测试包括产生频率信号的频率信号提供给预分频器IC上的直流控制信号的接收的步骤中,分频信号转换成转换后的信号具有预定的信号宽度和信号电平,检测一个 第一平均信号电平的值,并且在直流信号的形式提供第一平均值的IC测试器。 IC测试器被提供与所述第一平均值,并且执行通过使用第一平均值的预定操作的决定。

    Circuit arrangement comprising an end-of-life detector
    8.
    发明公开
    Circuit arrangement comprising an end-of-life detector 失效
    包含生命终端检测器的电路布置

    公开(公告)号:EP0547693A3

    公开(公告)日:1993-11-18

    申请号:EP92203864.1

    申请日:1992-12-10

    IPC分类号: G01R31/28

    CPC分类号: G01R31/316

    摘要: A circuit arrangement includes a wear detector which is proportioned or which operates so that it "wears faster" than the other parts of the circuit arrangement. To the wear detector there is connected an indicator which, when the wear detector ceases to function, indicates that the circuit arrangement is to be replaced.

    Method of testing control matrices for flat-panel displays
    10.
    发明公开
    Method of testing control matrices for flat-panel displays 失效
    Verfahren zum Testen von Steuermatrizen von Anzeigetafeln。

    公开(公告)号:EP0455406A1

    公开(公告)日:1991-11-06

    申请号:EP91303678.6

    申请日:1991-04-24

    申请人: GENRAD, INC.

    发明人: Hall, Henry P.

    IPC分类号: G01R31/28

    CPC分类号: G09G3/006 G01R31/316

    摘要: An AC signal source (26) in series with a variable DC source (34) drives a gate line of an LCD-display drive matrix (10), and current meters (28, 30, 32) monitor the resultant currents in the drain lines. By comparing the thus-measured transadmittance both with and without enabling values of the DC-source output, one can test the matrix (10) for defects.

    摘要翻译: 与可变DC源(34)串联的AC信号源(26)驱动LCD显示驱动矩阵(10)的栅极线,并且电流计(28,30,32)监视漏极线中的合成电流 。 通过比较如此测量的导纳两者,具有和不具有直流源输出的使能值,可以测试矩阵(10)的缺陷。