摘要:
A general purpose integrated circuit (I) tester (10) includes a set of channels (18), one for each input or output pin of an I device under test (DUT) (12). Each channel (18) is programmed by a host computer (22) to either supply a test signal to a DUT I/O pin (14, 16) or sample a DUT output signal appearing at the I/O pin (14, 16) and produce sample data representing its magnitude or logic state. The tester (10) also includes an amorphous logic circuit (ALC) (30) having a set of input and output terminals (28) and a programmable logic circuit interconnecting the input and output terminals. Some of the ALC input and output terminals (28) receive the sample data produced by each channel (18) and other ALC terminals send control signals directly to each channel (18). Other ALC terminals transmit data to the host computer (22).
摘要:
A test fixture for the testing of electronic assemblies (6). The test fixture including locating means to allow the electronic assembly or assemblies (6) placed therein to be located in the required test locations. The fixture also includes at least one heating means (2) which is located with respect to the electronic assemblies (6) to contact with one or a plurality of the components which are required to be heated during the testing of the electronic assembly (6).
摘要:
A programmable after-package, on-chip reference voltage trim circuit for an integrated circuit having a plurality of programmable trim cells generating a programmed sequence. A converter is provided to convert the bit sequence into a trim current. The trim current is added to an initial value of a reference voltage to be trimmed, as generated by the integrated circuit. Once the correct value of the trim current is determined, isolation circuitry is programmed to isolate the trim circuitry from the remainder of the IC, thereby freeing the logic and package pins associated with the IC for use by users of the IC. The preferred trim circuitry includes fuses which are blown in accordance with a bit value supplied to the trim cell to permanently fix a trim current value, once a best fit value is determined.
摘要:
A method for modeling semiconductors which utilizes a semiphysical device model (figure 45) coupled with an analytical thermal resistance model to self consistently solve for the channel temperature and internal charge/electric field structure of the semiconductor device.
摘要:
An analog electronic test probe (100) includes hundreds of inputs (105), each connected to two amplifiers (1130), each in a separate multiplexer stage (890, 891) on an integrated circuit (802). A programmer (121), responsive to a dial (145), shifts data through a shift register (1190) of latches, each of which is connected to one of the amplifiers (1130), activating the amplifier(s) connected to the selected input (105), thereby multiplexing it (them) to selected output(s) (129, 130). Similarly, the gain for each output may be selected. An outdisable circuit (100) connected to the outputs (871, 873, 874) of each multiplexer (810, 811, 812) and the outputs (872, 876) of each IC chip (802) causes each output to appear electrically as an open circuit when no input (105) associated with the multiplexer (810) or chip (802) is selected. This permits any number of multiplexers (810) and IC chips (802) to be daisy-chained together.
摘要:
An analog electronic test probe (100) includes hundreds of inputs (105), each connected to two amplifiers (1130), each in a separate multiplexer stage (890, 891) on an integrated circuit (802). A programmer (121), responsive to a dial (145), shifts data through a shift register (1190) of latches, each of which is connected to one of the amplifiers (1130), activating the amplifier(s) connected to the selected input (105), thereby multiplexing it (them) to selected output(s) (129, 130). Similarly, the gain for each output may be selected. An outdisable circuit (100) connected to the outputs (871, 873, 874) of each multiplexer (810, 811, 812) and the outputs (872, 876) of each IC chip (802) causes each output to appear electrically as an open circuit when no input (105) associated with the multiplexer (810) or chip (802) is selected. This permits any number of multiplexers (810) and IC chips (802) to be daisy-chained together.
摘要:
In a prescaler IC test method for carrying out a characterization test to decide whether or not a prescaler IC is normal by the use of an IC tester for carrying out a predetermined decision operation and a probe card for mounting said prescaler IC kept on a wafer, the prescaler IC carries out a frequency dividing operation on reception of a frequency signal to produce a frequency divided signal. The characterization test comprises the steps of generating the frequency signal to supply the frequency signal to the prescaler IC on reception of a direct current control signal, converting the frequency divided signal into a converted signal having a predetermined signal width and a signal level, detecting a first mean value of the signal level, and supplying the first mean value to the IC tester in the form of a direct current signal. The IC tester is supplied with the first mean value and carries out the predetermined decision operation by the use of the first mean value.
摘要:
A circuit arrangement includes a wear detector which is proportioned or which operates so that it "wears faster" than the other parts of the circuit arrangement. To the wear detector there is connected an indicator which, when the wear detector ceases to function, indicates that the circuit arrangement is to be replaced.
摘要:
An AC signal source (26) in series with a variable DC source (34) drives a gate line of an LCD-display drive matrix (10), and current meters (28, 30, 32) monitor the resultant currents in the drain lines. By comparing the thus-measured transadmittance both with and without enabling values of the DC-source output, one can test the matrix (10) for defects.