利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

7 条记录 (耗时 0.012 秒)

    FAULT TOLERANT DESIGN FOR LARGE AREA NITRIDE SEMICONDUCTOR DEVICES
    2.
    发明公开
    FAULT TOLERANT DESIGN FOR LARGE AREA NITRIDE SEMICONDUCTOR DEVICES 审中-公开
    大规模半导体半导体元件的容错设计

    公开(公告)号：EP3063792A4

    公开(公告)日：2016-09-28

    申请号：EP14859004

    申请日：2014-10-28

    申请人： GAN SYSTEMS INC

    发明人： KLOWAK GREGORY P ,  MCKNIGHT-MACNEIL CAMERON ,  TWEDDLE HOWARD ,  MIZAN AHMAD ,  SPRINGETT NIGEL

    IPC分类号： H01L21/66 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L29/417 ,  H01L29/778

    CPC分类号： H01L29/2003 ,  H01L22/14 ,  H01L22/22 ,  H01L29/41758 ,  H01L29/7786

    摘要： A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighbouring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid devices.

    FAULT TOLERANT DESIGN FOR LARGE AREA NITRIDE SEMICONDUCTOR DEVICES
    4.
    发明公开
    FAULT TOLERANT DESIGN FOR LARGE AREA NITRIDE SEMICONDUCTOR DEVICES 审中-公开
    FEHLERTOLERANTER ENTWURFFÜRGROSSFLÄCHIGEHALBLEITERBAUELEMENTE

    公开(公告)号：EP3063792A1

    公开(公告)日：2016-09-07

    申请号：EP14859004.5

    申请日：2014-10-28

    申请人： Gan Systems Inc.

    发明人： KLOWAK, Gregory P. ,  MCKNIGHT-MACNEIL, Cameron ,  TWEDDLE, Howard ,  MIZAN, Ahmad ,  SPRINGETT, Nigel

    IPC分类号： H01L29/778 ,  H01L21/66 ,  H01L29/41 ,  H01L27/02 ,  H01L29/20

    CPC分类号： H01L29/2003 ,  H01L22/14 ,  H01L22/22 ,  H01L29/41758 ,  H01L29/7786

    摘要： A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighbouring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid devices.

    摘要翻译： 提供了大面积氮化物半导体器件的容错设计，便于测试和隔离缺陷区域。 晶体管包括多个岛的阵列，每个岛包括有源区，源极和漏极以及栅电极。 每个岛的电极在阵列的至少一个方向上与相邻岛的电极电隔离。 提供源极，漏极和栅极接触焊盘，以实现每个岛的电气测试。 在岛的电测试以识别有缺陷的岛之后，形成覆盖的电连接以使源电极并联连接，并联的漏电极，并且互连栅电极以形成具有大栅极宽度Wg的公共栅电极。 选择性地向好的岛提供互连，同时电隔离有缺陷的岛。 这种方法使得制造大面积GaN器件（包括混合器件）在经济上是可行的。