公开(公告)号：EP4435848A1

公开(公告)日：2024-09-25

申请号：EP24159946.3

申请日：2024-02-27

申请人： Samsung Electronics Co., Ltd.

发明人： LEE, Doohyun ,  SHIN, Heonjong ,  PARK, Juneyoung ,  JANG, Jaeran

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L29/775

CPC分类号： H01L29/775 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/41725

摘要： An integrated circuit device, including a substrate having a plurality of device regions extending in a first horizontal direction, a plurality of gate electrodes on the plurality of device regions extending in a second horizontal direction that is orthogonal to the first horizontal direction, a plurality of source/drain regions each between a pair of gate electrodes adjacent to each other in the first horizontal direction among the plurality of gate electrodes, the plurality of source/drain regions being on portions of the plurality of device regions, a plurality of gate cut regions cutting the plurality of gate electrodes and extending in the first horizontal direction, and a plurality of contact structures including a plurality of contact body portions and a plurality of contact finger portions, the plurality of contact body portions filling the plurality of gate cut regions and extending in the first horizontal direction.

公开(公告)号：EP4421859A1

公开(公告)日：2024-08-28

申请号：EP24150929.8

申请日：2024-01-09

申请人： Samsung Electronics Co., Ltd.

发明人： YANG, Myung ,  HONG, Wonhyuk ,  JUNG, Myunghoon ,  LEE, Jongjin ,  BAEK, Jaejik ,  SEO, Kang-ill

IPC分类号： H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L29/775 ,  H01L27/06 ,  H01L21/822

CPC分类号： H01L21/76897 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0688 ,  H01L21/8221 ,  H01L29/41725 ,  H01L21/823481 ,  H01L29/775

摘要： A semiconductor device includes: at least one transistor comprising source/drain regions (113R, 113L) and 1st gate structure (115); a contact isolation layer (131) below the 1st gate structure; and a backside contact plug (107) connected to at least one (133R) of the 1st source/drain regions, wherein the backside contact plug is formed below the 1st source/drain region and extended to a region below the 1st gate structure (115), and isolated from the 1st gate structure by the contact isolation layer (131).

公开(公告)号：EP3915154B1

公开(公告)日：2024-07-03

申请号：EP19817555.6

申请日：2019-11-20

IPC分类号： H01L29/08 ,  H01L29/49 ,  H01L21/28 ,  H01L21/8234 ,  H10N70/20 ,  H10N70/00 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/402 ,  H01L29/78 ,  H10N70/235 ,  H10N70/253 ,  H10N70/823 ,  H10N70/8828

公开(公告)号：EP4386851A1

公开(公告)日：2024-06-19

申请号：EP23200754.2

申请日：2023-09-29

申请人： INTEL Corporation

发明人： JUN, Hwichan

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/10 ,  H01L29/161

CPC分类号： H01L29/0847 ,  H01L29/0673 ,  H01L29/41725 ,  H01L29/161 ,  B82Y10/00 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/1079 ,  H01L29/42392 ,  H01L29/66545 ,  H01L21/28518

摘要： Techniques are provided herein to form semiconductor devices having one or more epitaxial source or drain regions wrapped by a conductive contact to form an improved ohmic contact. A first semiconductor device includes a first semiconductor region extending between a first source or drain region and a second source or drain region, and a second semiconductor device includes a second semiconductor region extending between the first source or drain region and a third source or drain region. The first and second semiconductor devices include a subfin region adjacent to a dielectric layer. A conductive layer extends around the first source or drain region such that the conductive layer at least contacts the sidewalls of the first source or drain region and both upper and lower surfaces of the source or drain region. A dielectric layer is also present between the conductive contact and the subfin region.

公开(公告)号：EP4080582B1

公开(公告)日：2024-04-24

申请号：EP22169177.7

申请日：2022-04-21

IPC分类号： H01L29/778 ,  H01L29/417 ,  H01L29/06 ,  H01L29/20

CPC分类号： H01L29/7786 ,  H01L29/2003 ,  H01L29/0619 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/0653

公开(公告)号：EP4202552B1

公开(公告)日：2024-04-17

申请号：EP21217706.7

申请日：2021-12-24

IPC分类号： G03F7/20 ,  G03F9/00 ,  H01L21/66 ,  H01L23/544 ,  H01L29/423

CPC分类号： G03F7/70616 ,  G03F7/70683 ,  G03F7/70633 ,  H01L22/34 ,  G03F9/7084 ,  G03F9/7088 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/41725 ,  H01L29/78642

公开(公告)号：EP3413352A1

公开(公告)日：2018-12-12

申请号：EP18176875.5

申请日：2018-06-08

申请人： STMicroelectronics S.r.l.

发明人： IUCOLANO, Ferdinando ,  CHINI, Alessandro

IPC分类号： H01L29/778 ,  H01L21/336 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/207 ,  H01L29/20

CPC分类号： H01L29/778 ,  H01L29/0847 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/41725 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

摘要： HEMT (1; 21; 31; 51) including a buffer layer (4), a hole-supply layer (6) on the buffer layer (4), a heterostructure (7) on the hole-supply layer (6), and a source electrode (16). The hole-supply layer (6) is made of P-type doped semiconductor material, the buffer layer (4) is doped with carbon, and the source electrode (16) is in direct electrical contact with the hole-supply layer (6), such that the hole-supply layer (6) can be biased to facilitate the transport of holes from the hole-supply layer (6) to the buffer layer (4).

公开(公告)号：EP3227913A4

公开(公告)日：2018-07-25

申请号：EP15849828

申请日：2015-08-14

申请人： BOE TECHNOLOGY GROUP CO LTD ,  CHONGQING BOE OPTOELECTRONICS CO LTD

发明人： WANG WU ,  QIU HAIJUN ,  SHANG FEI ,  WANG GUOLEI

IPC分类号： H01L29/417 ,  H01L21/336 ,  H01L27/12 ,  H01L29/45 ,  H01L29/786

CPC分类号： H01L27/1288 ,  H01L21/0274 ,  H01L21/441 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1225 ,  H01L29/41725 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78615 ,  H01L29/78618 ,  H01L29/7869

摘要： Various embodiments provide a thin film transistor (TFT) device, a manufacturing method of the TFT device, and a display apparatus including the TFT device. An etch stop layer (ESL) material is formed on an active layer on a substrate. An electrical conductive layer material is formed on the ESL material for forming a source electrode and a drain electrode. The electrical conductive layer material is patterned to form a first portion of the source electrode containing a first via-hole through the source electrode, and to form a first portion of the drain electrode containing a second via-hole through the drain electrode. The ESL material is patterned to form an etch stop layer (ESL) pattern including a first ESL via-hole connecting to the first via-hole through the source electrode and including a second ESL via-hole connecting to the second via-hole through the drain electrode.

公开(公告)号：EP2559064A4

公开(公告)日：2018-07-18

申请号：EP11768308

申请日：2011-04-13

申请人： GAN SYSTEMS INC

发明人： ROBERTS JOHN ,  MIZAN AHMAD ,  PATTERSON GIRVAN ,  KLOWAK GREG

IPC分类号： H01L29/20 ,  H01L23/48 ,  H01L23/485 ,  H01L27/085 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/778

CPC分类号： H01L29/42316 ,  H01L24/05 ,  H01L24/13 ,  H01L27/0605 ,  H01L27/0629 ,  H01L27/085 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/7786 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13144 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/05552

摘要： A Gallium Nitride (GaN) series of devices—transistors and diodes are disclosed—that have greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The devices also include a simpler and superior flip chip connection scheme and a means to reduce the thermal resistance. A simplified fabrication process is disclosed and the layout scheme which uses island electrodes rather than finger electrodes is shown to increase the active area density by two to five times that of conventional interdigitated structures. Ultra low on resistance transistors and very low loss diodes can be built using the island topology. Specifically, the present disclosure provides a means to enhance cost/effective performance of all lateral GaN structures.

公开(公告)号：EP3198649A4

公开(公告)日：2018-05-16

申请号：EP14902679

申请日：2014-09-25

申请人： INTEL CORP

发明人： DASGUPTA SANSAPTAK ,  THEN HAN WUI ,  GARDNER SANAZ K ,  RADOSAVLJEVIC MARKO ,  SUNG SEUNG HOON ,  CHU-KUNG BENJAMIN ,  CHAU ROBERT S

IPC分类号： H01L21/20 ,  H01L29/778

CPC分类号： H01L29/7786 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/0657 ,  H01L29/41725 ,  H01L29/66462

摘要： III-N semiconductor heterostructures on III-N epitaxial islands laterally overgrown from a mesa of a silicon substrate. An IC may include a III-N semiconductor device disposed on the III-N epitaxial island overhanging the silicon mesa and may further include a silicon-based MOSFET monolithically integrated with the III-N device. Lateral epitaxial overgrowth from silicon mesas may provide III-N semiconductor regions of good crystal quality upon which transistors or other active semiconductor devices may be fabricated. Overhanging surfaces of III-N islands may provide multiple device layers on surfaces of differing polarity. Spacing between separate III-N islands may provide mechanical compliance to an IC including III-N semiconductor devices. Undercut of the silicon mesa may be utilized for transfer of III-N epitaxial islands to alternative substrates.