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公开(公告)号：EP3808698A1
公开(公告)日：2021-04-21
申请号：EP20199847.3
申请日：2020-10-02
Applicant: Hangzhou JWL Technology Inc.
Inventor： LI, Linping , SHENG, Jinghao , JIANG, Zhou
Abstract: Provided are a chip packaging method and a chip packaging structure. The passivation layer is arranged on the pads of the wafer, then the first bonding layer is formed on the passivation layer, and the second bonding layer is formed on the substrate. The substrate and the wafer are bonded and packaged together by bonding the first bonding layer and the second bonding layer. The pads are only used as a conductive structure, not as a bonding layer due to the passivation layer arranged between the pads and the bonding layer. The through silicon via is arranged at the position above the pad and avoiding the bonding layer, so as to connect the functional circuit region between the wafer and the substrate to the outside of the chip packaging structure.
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公开(公告)号：EP3787186A1
公开(公告)日：2021-03-03
申请号：EP20185122.7
申请日：2020-07-10
Applicant: Hangzhou JWL Technology Inc.
Inventor： LI, LINPING
Abstract: A method for packaging a chip and a chip package structure are provided. The method is used to package the chip including an acoustic filter. The packaging substrate and the device wafer are welded together, wherein the edge of the device wafer is chamfered, the packaging substrate is provided with a groove, the chamfered portion of device wafer is aligned with the groove on the substrate, and then a mask is disposed. The surface of the mask facing the device wafer is an inclined surface, forming a wedge-shaped opening. A package resin material is printed, wherein the package resin material falls into the groove through the inclined surface of the mask, and a package resin film is formed between the groove and the chamfer. The mask is removed along the first surface toward the second surface. The package resin is cured in a position where the resin film is located.
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