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1.发明公开MULTI-BIT MEMORY CELL HAVING ELECTRICALLY FLOATING BODY TRANSISTOR, AND METHOD OF PROGRAMMING AND READING SAME 审中-公开多单元电浮体晶体管和方法编程和读取SAME
公开(公告)号：EP1987520A4
公开(公告)日：2009-07-29
申请号：EP07750961
申请日：2007-02-15
发明人： CARMAN ERIC , OKHONIN SERGUEI , JONES MARK-ERIC
IPC分类号： G11C11/404 , G11C7/10 , G11C7/16 , G11C11/4076 , G11C11/56 , H01L27/108 , H01L29/78
CPC分类号： H01L29/7841 , G11C7/1006 , G11C7/16 , G11C11/404 , G11C11/565 , G11C2211/4016
摘要： Multi-bit memory cell and circuitry and techniques for reading, writing and/or operating a multi-bit memory cell (and memory cell array having a plurality of such memory cells) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The multi-bit memory cell stores more than one data bit (for example, two, three, four, five, six, etc ) and/or more than two data states (for example, three, four, five, six, etc. data or logic states. Notably, the memory cell array may comprise a portion of an integrated circuit device, for example, logic device (for example, a microprocessor) or a portion of a memory device (for example, a discrete memory)
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2.发明公开INTEGRATED CIRCUIT INCLUDING MEMORY ARRAY HAVING A SEGMENTED BIT LINE ARCHITECTURE AND METHOD OF CONTROLLING AND/OR OPERATING SAME 审中-公开具有存储阵列和分段双线结构的集成电路及其控制和/或操作方法
公开(公告)号：EP2041752A4
公开(公告)日：2009-08-12
申请号：EP07810300
申请日：2007-07-10
发明人： FISCH DAVID , BRON MICHEL
IPC分类号： G11C7/18
CPC分类号： H01L27/108 , G11C7/12 , G11C7/18 , G11C11/4097 , G11C2207/002 , G11C2211/4016 , H01L27/10802 , H01L29/7841
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3.发明授权METHOD AND CIRCUITRY TO GENERATE A REFERENCE CURRENT FOR READING A MEMORY CELL, AND DEVICE IMPLEMENTING SAME 有权方法与电路产生的参考流程用于读取存储单元与设备
公开(公告)号：EP1927111B1
公开(公告)日：2009-06-03
申请号：EP06805759.5
申请日：2006-09-19
发明人： BAUSER, Philippe
IPC分类号： G11C11/4099 , G11C7/14
CPC分类号： G11C7/14 , G11C11/4099
摘要： There are many inventions disclosed herein. In one aspect, the present inventions are directed to methods and circuitry to control, adjust, determine and/or modify the absolute and/or relative positioning or location (i.e., absolute or relative amount) of reference current which is employed by sensing circuitry to sense the data state of a memory cell during a read operation of one or more memory cells. The control, adjustment, determination and/or modification of the reference current levels may be implemented using many different, distinct and/or diverse techniques and circuitry, including both analog and digital techniques and circuitry.
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4.发明公开INTEGRATED CIRCUIT INCLUDING MEMORY ARRAY HAVING A SEGMENTED BIT LINE ARCHITECTURE AND METHOD OF CONTROLLING AND/OR OPERATING SAME 审中-公开用于控制和/或业务存储器阵列和分段位线的体系结构和方法集成电路
公开(公告)号：EP2041752A2
公开(公告)日：2009-04-01
申请号：EP07810300.9
申请日：2007-07-10
发明人： FISCH, David , BRON, Michel
CPC分类号： H01L27/108 , G11C7/12 , G11C7/18 , G11C11/4097 , G11C2207/002 , G11C2211/4016 , H01L27/10802 , H01L29/7841
摘要： An integrated memory circuit device having a memory cell array (102) including a plurality of bit lines (e.g., 32a, 32b) and a plurality of bit line segments (e.g., 32a1, 32b1) wherein each bit line segment is coupled to an associated bit line (32a, 32b). The memory cell array (102) further includes a plurality of memory cells (12), wherein each memory cell (12) includes a transistor (14) having a first region, a second region, a body region, and a gate coupled to an associated word line (28) via an associated word line segment. A first group of memory cells (12) is coupled to the first bit line (32a) via the first bit line segment (32a1) and a second group of memory cells (12) is coupled to the second bit line (32b) via the second bit line segment (32b1). A plurality of isolation circuits (104), disposed between each bit line segment (32a1, 32b1) and its associated bit line (32a, 32b), responsively connect the associated bit line segment to or disconnect the associated bit line segment (32a1, 32b1) from the associated bit line (32a, 32b).
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