公开(公告)号：EP3049956B1

公开(公告)日：2018-10-10

申请号：EP14891599.4

申请日：2014-12-14

申请人： VIA Alliance Semiconductor Co., Ltd.

发明人： COL, Gerard, M. ,  EDDY, Colin ,  HENRY, G., Glenn

IPC分类号： G06F15/163

CPC分类号： G06F9/226 ,  G06F1/3243 ,  G06F9/30043 ,  G06F9/38 ,  G06F9/3836 ,  G06F12/0875 ,  G06F15/163 ,  G06F2212/452

摘要： An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include an input/output (I/O) unit, configured to perform I/O operations via an I/O bus coupling an out-of-order processor to I/O resources.

公开(公告)号：EP3371704A1

公开(公告)日：2018-09-12

申请号：EP16862765.1

申请日：2016-10-31

申请人： Sony Interactive Entertainment LLC

发明人： CERNY, Mark Evan ,  SIMPSON, David

IPC分类号： G06F11/22 ,  G06F12/08 ,  G06F15/177 ,  G06F15/16

CPC分类号： G06F11/3668 ,  G06F9/3001 ,  G06F9/30079 ,  G06F9/46 ,  G06F12/084 ,  G06F12/0875 ,  G06F12/1045 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/62

摘要： A device may be run in a timing testing mode in which the device is configured to disrupt timing of processing that takes place on the one or more processors while running an application with the one or more processors. The application may be tested for errors while the device is running in the timing testing mode

公开(公告)号：EP3367235A1

公开(公告)日：2018-08-29

申请号：EP17159096.1

申请日：2017-03-03

申请人： Advanced Micro Devices, Inc.

发明人： FOWLER, Mark ,  EMBERLING, Brian

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30043 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3834 ,  G06F9/3851 ,  G06F12/0875 ,  G06F2212/452

摘要： Systems, apparatuses, and methods for maintaining separate pending load and store counters are disclosed herein. In one embodiment, a system includes at least one execution unit, a memory subsystem, and a pair of counters for each thread of execution. In one embodiment, the system implements a software based approach for managing dependencies between instructions. In one embodiment, the execution unit(s) maintains counters to support the software-based approach for managing dependencies between instructions. The execution unit(s) are configured to execute instructions that are used to manage the dependencies during run-time. In one embodiment, the execution unit(s) execute wait instructions to wait until a given counter is equal to a specified value before continuing to execute the instruction sequence.

公开(公告)号：EP3350719A1

公开(公告)日：2018-07-25

申请号：EP16775383.9

申请日：2016-09-13

申请人： Microsoft Technology Licensing, LLC

发明人： BURGER, Douglas C. ,  SMITH, Aaron L.

IPC分类号： G06F15/78 ,  G06F9/38

CPC分类号： G06F9/3016 ,  G06F9/268 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/466 ,  G06F9/528 ,  G06F11/36 ,  G06F11/3648 ,  G06F11/3656 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/4221 ,  G06F15/7867 ,  G06F15/80 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.

公开(公告)号：EP3350707A1

公开(公告)日：2018-07-25

申请号：EP16775377.1

申请日：2016-09-13

申请人： Microsoft Technology Licensing, LLC

发明人： BURGER, Douglas C. ,  SMITH, Aaron L.

IPC分类号： G06F12/0806 ,  G06F9/38

CPC分类号： G06F9/3016 ,  G06F9/268 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/466 ,  G06F9/528 ,  G06F11/36 ,  G06F11/3648 ,  G06F11/3656 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/4221 ,  G06F15/7867 ,  G06F15/80 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.

公开(公告)号：EP3350706A1

公开(公告)日：2018-07-25

申请号：EP16775374.8

申请日：2016-09-13

申请人： Microsoft Technology Licensing, LLC

发明人： BURGER, Douglas C. ,  SMITH, Aaron L.

IPC分类号： G06F12/0806 ,  G06F9/38

CPC分类号： G06F9/3016 ,  G06F9/268 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/466 ,  G06F9/528 ,  G06F11/36 ,  G06F11/3648 ,  G06F11/3656 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/4221 ,  G06F15/7867 ,  G06F15/80 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.

公开(公告)号：EP3350688A1

公开(公告)日：2018-07-25

申请号：EP16775905.9

申请日：2016-09-13

申请人： Microsoft Technology Licensing, LLC

发明人： BURGER, Douglas C. ,  SMITH, Aaron L.

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3016 ,  G06F9/268 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/466 ,  G06F9/528 ,  G06F11/36 ,  G06F11/3648 ,  G06F11/3656 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/4221 ,  G06F15/7867 ,  G06F15/80 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.

公开(公告)号：EP3146434B1

公开(公告)日：2018-06-20

申请号：EP15726846.7

申请日：2015-05-21

申请人： Qualcomm Incorporated

发明人： HEDDES, Mattheus, Cornelis Antonius Adrianus ,  VAIDHYANATHAN, Natarajan ,  VERRILLI, Colin Beaton

IPC分类号： G06F12/0811 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/1081 ,  G06F12/02

CPC分类号： G06F12/1081 ,  G06F12/023 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/0833 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/2532 ,  G06F2212/401 ,  G06F2212/452 ,  G06F2212/62 ,  G06F2212/621 ,  G06F2212/622 ,  Y02D10/13

摘要： Providing memory bandwidth compression using compressed memory controllers (CMCs) in a central processing unit (CPU)-based system is disclosed. In this regard, in some aspects, a CMC is configured to receive a memory read request to a physical address in a system memory, and read a compression indicator (CI) for the physical address from a master directory and/or from error correcting code (ECC) bits of the physical address. Based on the CI, the CMC determines a number of memory blocks to be read for the memory read request, and reads the determined number of memory blocks. In some aspects, a CMC is configured to receive a memory write request to a physical address in the system memory, and generate a CI for write data based on a compression pattern of the write data. The CMC updates the master directory and/or the ECC bits of the physical address with the generated CI.

公开(公告)号：EP3333700A1

公开(公告)日：2018-06-13

申请号：EP16203863.2

申请日：2016-12-13

申请人： Advanced Micro Devices, Inc.

发明人： SUGGS, David

IPC分类号： G06F9/38 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0855 ,  G06F9/30

CPC分类号： G06F9/3808 ,  G06F9/3012 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/30174 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3816 ,  G06F9/382 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3846 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3885 ,  G06F9/3891 ,  G06F12/0855 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/1024 ,  G06F2212/452 ,  G06F2212/6028

摘要： A system and method for using an operation (op) cache is disclosed. The system and method include an op cache for caching previously decoded instructions. The op cache includes a plurality of physically indexed and tagged instructions allowing sharing of instructions between threads. The op cache is chained through multiple ways allowing service of a plurality of instructions in a cache line. The op cache is stored between a shared operation storage and immediate/displacement storage to maximize capacity.

公开(公告)号：EP2132899B1

公开(公告)日：2018-06-06

申请号：EP08744319.8

申请日：2008-03-25

申请人： Intel Corporation

发明人： GUERON, Shay ,  FEGHALI, Wajdi, K. ,  GOPAL, Vinodh ,  RAGHUNANDAN, Makaram ,  DIXON, Martin, G. ,  CHENNUPATY, Srinivas ,  KOUNAVIS, Michael, E.

IPC分类号： H04L9/06 ,  H04L9/08 ,  G06F3/06 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/14 ,  G06F21/60 ,  G11C7/10

CPC分类号： H04L9/0631 ,  G06F3/0623 ,  G06F3/0665 ,  G06F3/0689 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30145 ,  G06F9/30178 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3887 ,  G06F9/3895 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1408 ,  G06F21/602 ,  G06F2212/1052 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2212/454 ,  G06F2212/602 ,  G11C7/1072 ,  H04L9/0816 ,  H04L9/0861 ,  H04L2209/12 ,  H04L2209/24

摘要： Methods and devices for use with the advanced encryption standard (AES) are presented including a processor comprising a decode unit to decode a single round encryption instruction to perform an AES single round encryption operation, wherein the single round encryption instruction specifies a destination register to store 128-bit input data and a source register to store a 128-bit round key; and an execution unit to execute micro-operations based on the single round encryption instruction, wherein the execution unit is to receive the 128-bit input data and the 128-bit round key, and wherein the execution unit is to perform the AES single round encryption operation on the 128-bit input data using the round key and to store 128-bit result data in the destination register.