摘要:
A method of processing in a bridge interface controller data write requests corresponding to a specified address, the method comprising testing whether a cache in the bridge interface controller contains a cache line corresponding to the specified address, writing to the cache if the cache contains a cache line corresponding to the specified address, writing the cache line to memory if the last byte of the cache line is written and then freeing the cache line, if the cache line corresponding to the specified address is not within the cache writing the data into an empty cache line in the cache.
摘要:
A method of processing in a bridge interface controller data write requests corresponding to a specified address, the method comprising
testing whether a cache in the bridge interface controller contains a cache line corresponding to the specified address, writing to the cache if the cache contains a cache line corresponding to the specified address, writing the cache line to memory if the last byte of the cache line is written and then freeing the cache line, if the cache line corresponding to the specified address is not within the cache writing the data into an empty cache line in the cache.
摘要:
A computer system (310; 3010) having a reduced power control circuit (311; 3011) which operates in a first reduced power state in which power is reduced to at least one peripheral (318, 321, 322, 327, 331; 3021, 3022, 3023, 3026, 3028, 3031) and in a second reduced power state in which the operating speed of said CPU (311; 3011) is reduced to further limit power to said computer system (310; 3010).
摘要:
The invention relates to an arbitration means for determining access to a system by a plurality of functional units. Each functional unit has mask latch means for receiving and storing an arbitration mask having an entry representing the relative priority of the functional unit. The arbitration means comprises a plurality of arbitration lines, arbitration latch means having unshifted inputs connected from the arbitration lines to receive and store arbitration signals asserted by the functional units, and control means. The control means determines the priority of the functional unit from a comparison of the latched arbitration signals and the mask. The control means asserts an arbitration signal until the functional unit is the highest priority member of the group, asserts control of the system bus when the functional unit is the highest priority member of the group and ceases to assert the functional unit arbitration signal at completion of the bus operation.
摘要:
In a data processing system including a plurality of functional units containing addressable storage locations, means in each of the plurality of functional units for mapping addresses of the system address space to the addressable storage locations of the functional units, comprising:
address map means for storing mapping entries, each mapping entry corresponding to at least one addressable storage location in the functional unit, and to at least one address of the address space of the system, and containing information relating the at least one address of the address space of the system to the at least one storage location in the functional unit; and means responsive to an address to read a corresponding mapping entry from the address map means and determine the corresponding storage location in the functional unit.
摘要:
A computer system (310; 3010) having a reduced power control circuit (311; 3011) which operates in a first reduced power state in which power is reduced to at least one peripheral (318, 321, 322, 327, 331; 3021, 3022, 3023, 3026, 3028, 3031) and in a second reduced power state in which the operating speed of said CPU (311; 3011) is reduced to further limit power to said computer system (310; 3010).
摘要:
The invention relates to an arbitration means for determining access to a system by a plurality of functional units. Each functional unit has mask latch means for receiving and storing an arbitration mask having an entry representing the relative priority of the functional unit. The arbitration means comprises a plurality of arbitration lines, arbitration latch means having unshifted inputs connected from the arbitration lines to receive and store arbitration signals asserted by the functional units, and control means. The control means determines the priority of the functional unit from a comparison of the latched arbitration signals and the mask. The control means asserts an arbitration signal until the functional unit is the highest priority member of the group, asserts control of the system bus when the functional unit is the highest priority member of the group and ceases to assert the functional unit arbitration signal at completion of the bus operation.
摘要:
The system comprises two memories, a display, and control circuitry. The first memory is used to store image information for display, while the second memory is used to receive information, from the first memory, when required. This transfer is initiated by the control circuitry which also reduces power to the first memory, after the information has been transferred. The control circuitry also restores power to the first memory, when required, and initiates the transfer of information from the second memory back to the first.
摘要:
A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.