公开(公告)号：EP2876072B1

公开(公告)日：2018-03-14

申请号：EP14188680.4

申请日：2014-10-13

申请人： RGB Systems Inc.

发明人： Soper, Matthew

IPC分类号： B65H75/36 ,  B65H75/44 ,  H02G11/00

CPC分类号： B65H75/368 ,  B65H75/4423 ,  B65H75/4439 ,  B65H2701/34 ,  H02G11/003

摘要： The present invention is a speed control for a cable retractor. The cable retractor with which the speed control is used comprises a pulley (1165) that engages a cable (1035) that may be extended and retracted. A friction element (1140) configured to adjustably contact the cable (1035) adjacent to the pulley (1165) is attached to a movable linkage. The movement of the linkage is constrained to move along a predetermined path such that movement of the linkage along the path alters the distance between the friction element (1140) and the pulley (1165). In one or more embodiments a cantilevered spring (1055) is attached to the linkage. An adjustable control, for example a thumbscrew (1060), is configured to move the spring in relation to the linkage in a manner that alters the position of the friction element with respect to the cable and/or the pressure exerted by the friction element on the cable.

公开(公告)号：EP1917813B1

公开(公告)日：2015-07-01

申请号：EP06765262.8

申请日：2006-08-11

申请人： RGB Systems, Inc.

发明人： SMITH, Peter, Lionel

IPC分类号： H04N19/176 ,  H04N19/70

CPC分类号： H04N19/68 ,  H04N19/107 ,  H04N19/13 ,  H04N19/132 ,  H04N19/17 ,  H04N19/174 ,  H04N19/176 ,  H04N19/182 ,  H04N19/186 ,  H04N19/1883 ,  H04N19/33 ,  H04N19/42 ,  H04N19/423 ,  H04N19/507 ,  H04N19/51 ,  H04N19/61 ,  H04N19/63 ,  H04N19/635 ,  H04N19/645 ,  H04N19/647 ,  H04N19/66 ,  H04N19/70 ,  H04N19/86 ,  H04N19/89 ,  H04N19/96

摘要： Methods of data encoding using trees formed with logic gates are described which lead to spatial compression of image data. Data encoding is achieved using a five-level wavelet transform, such as the Haar or the 2/10 transform. A dual transform engine is used, the first and engine being used for the first part of the first-level transform, the second part of the first-level transform and the subsequent-level transforms being performed by the second transform engine within a time interval which is less than or equal to the time taken by the first transform engine to effect the part-transform. Each bit plane of the resulting coefficients is then encoded by forming a tree structure from the bits and OR logical combinations thereof. Redundant data are removed from the resulting tree structure, and further data can be removed by using a predetermined compression profile. The resulting blocks of compressed data are of variable length and are packaged with sync words and index words for transmission so that the location and identity of the transformed data blocks can be determined from the received signal.

公开(公告)号：EP2716062A4

公开(公告)日：2014-12-17

申请号：EP12789123

申请日：2012-05-23

申请人： RGB SYSTEMS INC

发明人： STEWART WILLIAM CAMERON JR ,  HATLEY JEFF ,  HUDSON MICHAEL ,  FRERICHS LARRY

IPC分类号： H04R1/02

CPC分类号： H04R1/026 ,  H04R2201/021

公开(公告)号：EP2721837A1

公开(公告)日：2014-04-23

申请号：EP12800877.8

申请日：2012-06-13

申请人： RGB Systems, Inc.

发明人： STEWART, William, C., Jr. ,  HUDSON, Michael ,  FRERICHS, Larry ,  STRONG, Clinton ,  GAMMON, Weldon

IPC分类号： H04R1/02

CPC分类号： H04R1/025 ,  H04R1/026 ,  H04R2201/021

摘要： The present invention comprises a method and apparatus for installing a tile-mounted ceiling speaker that combines the ease of installation of a lay-in speaker system with the visual appearance of a tile-mounted speaker system. In one or more embodiments, the method of the present invention comprises forming an appropriately-sized hole in a ceiling tile, laying an integrated back box and support frame on top of the ceiling tile, connecting wires from an external audio source to terminals provided at the back box, connecting wires provided on the inside of the back box to a loudspeaker cartridge, inserting the loudspeaker cartridge into the hole in the ceiling tile from below, fastening the loudspeaker cartridge to the support frame, and fastening a grille to the loudspeaker cartridge.

公开(公告)号：EP2127078B1

公开(公告)日：2012-09-26

申请号：EP08713985.3

申请日：2008-01-24

申请人： RGB Systems, Inc.

发明人： MENDENHALL, Eric

IPC分类号： H03K4/06

CPC分类号： H03K4/90 ,  H03F3/217 ,  H03K4/06 ,  H03K5/06

公开(公告)号：EP2127078A4

公开(公告)日：2011-07-27

申请号：EP08713985

申请日：2008-01-24

申请人： RGB SYSTEMS INC

发明人： MENDENHALL ERIC

IPC分类号： H03K4/06

CPC分类号： H03K4/90 ,  H03F3/217 ,  H03K4/06 ,  H03K5/06

公开(公告)号：EP1312070B1

公开(公告)日：2010-06-02

申请号：EP00990420.2

申请日：2000-12-29

申请人： RGB Systems, Inc.

发明人： TARACI, Brian, Richard ,  TROUNG, Duy, Duc

IPC分类号： G09G5/12 ,  G09G5/18

CPC分类号： G09G5/006 ,  H03L7/235 ,  H04N5/126 ,  H04N5/268 ,  H04N5/4401 ,  H04N5/46 ,  H04N5/74 ,  H04N7/012 ,  H04N7/104 ,  H04N9/641 ,  H04N9/642 ,  H04N21/4113

摘要： This invention describes a method and apparatus for vertically locking input and output video frame rates. The output vertical sync pulse is locked in phase with the input vertical sync pulse, regardless of the input format and frequency. The output resolution, horizontal refresh rate, and delay are all user selectable. Two Phase Locked Loops are connected in series to achive vertical lock between the input and output frames. Locking the vertical sync pulses between the input and output frames will eliminate mixing of pixels from different input frames in one output frame. The first Phase Locked Loop generates the output pixel clock required to satisfy the user's display preferences but may not precisely represent the desired output pixel clock required for frame locking because current Phase Locked Loops use integer dividers. A second Phase Locked Loop adjusts its output, which is the reference frequency to the first Phase Locked Loop, until a lock is achieved.

公开(公告)号：EP3961921A1

公开(公告)日：2022-03-02

申请号：EP21192551.6

申请日：2021-08-23

申请人： RGB Systems, Inc.

发明人： Mendenhall, Eric

IPC分类号： H03F3/183 ,  H03F3/217

摘要： An audio amplifier that implements current mode control without the use of an explicit or separate current mode sensor is disclosed. The audio amplifier may include a pair of feedback loops that provide current from a node located before an inductor of an output filter and current from a node located after the inductor of the output filter to an integrator circuit. The integrator circuit may be formed from existing circuitry of the audio amplifier controller. Thus, current mode control can be implemented without a separate current mode sensor.

公开(公告)号：EP3624336A3

公开(公告)日：2020-08-26

申请号：EP19193212.8

申请日：2019-08-22

申请人： RGB Systems, Inc.

发明人： Mendenhall, Eric

IPC分类号： H03F1/26 ,  H03F1/32 ,  H03F3/187 ,  H03G3/30 ,  H03G11/04

摘要： A voltage controlled amplifier with an amplitude limiting circuit, such as a clip limiter, that is separate from the signal path on which the input signal is received by a power amplifier can reduce both noise and power expenditure of the voltage controlled amplifier. The amplitude limiting circuit can include a transistor network that is controlled by a pair of utility operational amplifiers. These utility amplifiers may use less current than the audio amplifier of the voltage controlled amplifier. Further, the transistor network can be deactivated when a signal supplied to the voltage controlled amplifier is below a clipping or other voltage limiting threshold.

公开(公告)号：EP2928189A1

公开(公告)日：2015-10-07

申请号：EP15164542.1

申请日：2006-08-11

申请人： RGB Systems, Inc.

发明人： Smith, Peter Lionel

IPC分类号： H04N19/176 ,  H04N19/70 ,  H04N19/64 ,  H04N19/63 ,  H04N19/61 ,  H04N19/107 ,  H04N19/132 ,  H04N19/17 ,  H04N19/635 ,  H04N19/42 ,  H04N19/89 ,  H04N19/645 ,  H04N19/86 ,  H04N19/507 ,  H04N19/68

CPC分类号： H04N19/68 ,  H04N19/107 ,  H04N19/13 ,  H04N19/132 ,  H04N19/17 ,  H04N19/174 ,  H04N19/176 ,  H04N19/182 ,  H04N19/186 ,  H04N19/1883 ,  H04N19/33 ,  H04N19/42 ,  H04N19/423 ,  H04N19/507 ,  H04N19/51 ,  H04N19/61 ,  H04N19/63 ,  H04N19/635 ,  H04N19/645 ,  H04N19/647 ,  H04N19/66 ,  H04N19/70 ,  H04N19/86 ,  H04N19/89 ,  H04N19/96

摘要： Methods of data encoding using trees formed with logic gates are described which lead to spatial compression of image data. Data encoding is achieved using a five-level wavelet transform, such as the Haar or the 2/10 transform. A dual transform engine is used, the first and engine being used for the first part of the first-level transform, the second part of the first-level transform and the subsequent-level transforms being performed by the second transform engine within a time interval which is less than or equal to the time taken by the first transform engine to effect the part-transform. Each bit plane of the resulting coefficients is then encoded by forming a tree structure from the bits and OR logical combinations thereof. Redundant data are removed from the resulting tree structure, and further data can be removed by using a predetermined compression profile. The resulting blocks of compressed data are of variable length and are packaged with sync words and index words for transmission so that the location and identity of the transformed data blocks can be determined from the received signal.

摘要翻译： 描述了使用由逻辑门形成的树的数据编码方法，其导致图像数据的空间压缩。 数据编码通过使用五级小波变换（如Haar或2/10变换）来实现。 使用双变换引擎，第一和引擎用于第一级变换的第一部分，第一级变换的第二部分和后续级变换由第二变换引擎在一段时间间隔内执行 这小于或等于第一变换引擎进行部分变换所花费的时间。 然后通过根据其比特和OR逻辑组合来形成树结构来对结果系数的每个比特平面进行编码。 从生成的树结构中删除冗余数据，并且可以使用预定的压缩配置文件删除更多数据。 所得到的压缩数据块具有可变长度，并且与同步字和索引字一起封装以用于传输，从而可以根据接收到的信号确定经变换的数据块的位置和身份。