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1.发明公开COMPENSATING FOR DIFFERENCES BETWEEN CLOCK SIGNALS 审中-公开AUSGLEICH VON DIFFERENZEN ZWISCHEN TAKTSIGNALEN
公开(公告)号：EP1419579A4
公开(公告)日：2004-10-06
申请号：EP02800315
申请日：2002-08-22
发明人： DORMITZER PAUL , ENGELSE WILLEM , ROBIDOUX RAYMOND
CPC分类号： H03L7/06 , H04L7/0008
摘要： A clock compensation circuit 102 is provided. The circuit comprises a clock synchronization circuit 110 coupled to receive an input clock signal 101-1, wherein the clock synchronization circuit generates a master clock signal and produces a plurality of internal logic clock signals 105. The circuit further comprises a phase comparator 120s coupled to receive one of the plurality of internal logic clock signals and a sample clock PHYRET from an associated receiver, wherein the phase comparator generates a control signal based on a phase comparison between the sample clock and the one of the plurality of internal logic clock signals and a down converter channel 115s coupled to receive each of the plurality of internal logic clock signals and the control signal and to pass data in phase with the sample clock using the internal logic clock signal based on the control signal.
摘要翻译： 提供时钟补偿电路102。 该电路包括时钟同步电路110，其被耦合以接收输入时钟信号101-1，其中时钟同步电路产生主时钟信号并产生多个内部逻辑时钟信号105.该电路还包括相位比较器120s，其耦合到 从相关联的接收器接收所述多个内部逻辑时钟信号和采样时钟PHYRET中的一个，其中，所述相位比较器基于所述采样时钟与所述多个内部逻辑时钟信号中的所述一个之间的相位比较来生成控制信号， 下变频器通道115s，被耦合以接收多个内部逻辑时钟信号和控制信号中的每一个，并且基于控制信号使用内部逻辑时钟信号使数据与采样时钟同相地传递。
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公开(公告)号：EP1425857A4
公开(公告)日：2004-12-15
申请号：EP02773190
申请日：2002-08-14
发明人： UNGER DAVID , ENGELSE WILLEM , CORLEY WILLIAM , DAVIES DAVID , DORMITZER PAUL , ROBIDOUX RAYMOND
CPC分类号： H03H17/0685 , H03D7/00 , H03H17/0657 , H03H17/0664
摘要： A digital down converter (100) is provided. The digital down converter (100) includes an input adapted (102) to receive an input signal (101), a mixer circuit (104) coupled to the input to down converter the input signal, and a decimation circuit (115) coupled to the mixer. The decimation circuit is adapted to decimate down converter signal by a factor selected based on a characteristic of the input signal. The digital down converter further includes a signal conditioning circuit (118), coupled to the output of the decimation circuit (115), that conditions the decimated signal, an interpolator (120) coupled to the decimation circuit, that increase the number of samples in the conditioned signal, and a second mixer circuit (126), coupled to the interpolator, the second mixer circuit adapted to modulate a carried with the conditioned signal.
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