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公开(公告)号：EP0341897A2
公开(公告)日：1989-11-15
申请号：EP89304467.7
申请日：1989-05-04
IPC分类号： G06F17/30
CPC分类号： G06F17/30982 , G11C15/04
摘要： A content addressable memory system includes a plurality of memory cells arranged in rows and columns in an array of N bit words by M word cells, a plurality of word lines extending through the array for addressing different words in the memory cells, each of the words comprising a plurality of adjacent cells extending in a first direction in the array, a plurality of match lines extending through the array in parallel with the word lines in the first direction, a plurality of bit lines extending through the array in a second direction perpendicular to the first direction, each of the bit lines communicating with the cells in one of the columns extending in the second direction, and a pair of registers connected to the bit lines for performing masking operations on bits in the array.
摘要翻译： 内容可寻址存储器系统包括以M字单元排列成N字列阵列中的行和列的多个存储单元，多个字线延伸穿过该阵列，用于寻址存储单元中的不同字，每个字 包括沿所述阵列中的第一方向延伸的多个相邻单元，沿着所述第一方向与所述字线平行延伸穿过所述阵列的多个匹配线，沿与所述第一方向垂直的第二方向延伸穿过所述阵列的多个位线 第一方向，每个位线与沿第二方向延伸的一列中的单元通信，以及一对连接到位线的寄存器，用于对阵列中的位进行掩蔽操作。
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公开(公告)号：EP0341899B1
公开(公告)日：1993-07-14
申请号：EP89304469.3
申请日：1989-05-04
IPC分类号： G11C15/00
CPC分类号： G06F17/30982 , G11C15/04
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公开(公告)号：EP0341896A3
公开(公告)日：1992-10-21
申请号：EP89304466.9
申请日：1989-05-04
CPC分类号： G06F17/30982
摘要： A content addressable memory system includes an array of memory cells arranged in rows and columns in an array of N bit cells by M words, with N bits per word, an I/O bus having a bit capacity S which is a submultiple of N, a mode generator for generating a plurality of commands, the commands including a command write command, a data write command, a data read command, and a status read command, the command write and the status read commands being encodable in S bits or less, and multiplexing means for supplying selected ones of the commands to the I/O bus.
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公开(公告)号：EP0200500A3
公开(公告)日：1989-03-08
申请号：EP86303148.0
申请日：1986-04-25
发明人： Chuang, Patrick T. , Shu, Lee-Lean
IPC分类号： G11C11/24
CPC分类号： G11C11/4094 , G11C11/4074
摘要： A biasing scheme for a CMOS memory array. The bit lines and dummy bit lines in the array are precharged to Vcc/2, where Vcc is the externally supplied voltage level. The capacitor plates of the memory cells and dummy cells are biased to V cc /2 and the N well is biased to 1.6 V cc . The biasing scheme reduces, or eliminates, the effects of precharge current spike, differential sense amp voltage reduction, sense level disturbance and charge injection. A bit line emulating bias voltage generator minimizes power dissipation.
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公开(公告)号：EP0341897B1
公开(公告)日：1997-07-30
申请号：EP89304467.7
申请日：1989-05-04
IPC分类号： G06F17/30
CPC分类号： G06F17/30982 , G11C15/04
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公开(公告)号：EP0341899A1
公开(公告)日：1989-11-15
申请号：EP89304469.3
申请日：1989-05-04
IPC分类号： G11C15/00
CPC分类号： G06F17/30982 , G11C15/04
摘要： A content addressable memory array (11) includes an array of cells containing bits configured in N bits for each word, a first one of the bits in each of the words being a skip bit, the array (11) being searched on the basis of the contents of the words to locate selected words, a second one of the bits in each word being identified as an empty bit, means for examining the words to detect the presence therein of skip bits, means for examining the words to detect the presence therein of empty bits, and means responsive to detection of one of the skip bits in one of the words for eliminating the word containing the detected skip bit from said search.
摘要翻译： 内容可寻址存储器阵列（11）包括一个单元阵列，其中包含用于每个单词的N位配置的位，每个单词中的第一位是跳过位，所述阵列（11）基于 用于定位所选择的单词的单词的内容，每个单词中的第二位被识别为空位，用于检查词以检测其中存在跳过位的装置，用于检查词以检测其中存在的装置 以及响应于检测一个字中的一个跳跃位的装置，用于从所述搜索中消除包含检测到的跳过位的字。
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公开(公告)号：EP0200500A2
公开(公告)日：1986-11-05
申请号：EP86303148.0
申请日：1986-04-25
发明人： Chuang, Patrick T. , Shu, Lee-Lean
IPC分类号： G11C11/24
CPC分类号： G11C11/4094 , G11C11/4074
摘要： A biasing scheme for a CMOS memory array. The bit lines and dummy bit lines in the array are precharged to Vcc/2, where Vcc is the externally supplied voltage level. The capacitor plates of the memory cells and dummy cells are biased to V cc /2 and the N well is biased to 1.6 V cc . The biasing scheme reduces, or eliminates, the effects of precharge current spike, differential sense amp voltage reduction, sense level disturbance and charge injection. A bit line emulating bias voltage generator minimizes power dissipation.
摘要翻译： CMOS存储器阵列的偏置方案。 阵列中的位线和虚拟位线被预充电到Vcc / 2，其中Vcc是外部提供的电压电平。 存储器单元和伪单元的电容器极板偏置到Vcc / 2，并且N阱偏置到1.6Vcc。 该偏置方案降低或消除了预充电电流尖峰，差分读出放大器电压降低，感应电平干扰和电荷注入的影响。 仿真偏置电压发生器的位线可以最大限度地降低功耗。
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公开(公告)号：EP0341897A3
公开(公告)日：1992-10-28
申请号：EP89304467.7
申请日：1989-05-04
IPC分类号： G06F17/30
CPC分类号： G06F17/30982 , G11C15/04
摘要： A content addressable memory system includes a plurality of memory cells arranged in rows and columns in an array of N bit words by M word cells, a plurality of word lines extending through the array for addressing different words in the memory cells, each of the words comprising a plurality of adjacent cells extending in a first direction in the array, a plurality of match lines extending through the array in parallel with the word lines in the first direction, a plurality of bit lines extending through the array in a second direction perpendicular to the first direction, each of the bit lines communicating with the cells in one of the columns extending in the second direction, and a pair of registers connected to the bit lines for performing masking operations on bits in the array.
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公开(公告)号：EP0341896A2
公开(公告)日：1989-11-15
申请号：EP89304466.9
申请日：1989-05-04
CPC分类号： G06F17/30982
摘要： A content addressable memory system includes an array of memory cells arranged in rows and columns in an array of N bit cells by M words, with N bits per word, an I/O bus having a bit capacity S which is a submultiple of N, a mode generator for generating a plurality of commands, the commands including a command write command, a data write command, a data read command, and a status read command, the command write and the status read commands being encodable in S bits or less, and multiplexing means for supplying selected ones of the commands to the I/O bus.
摘要翻译： 内容可寻址存储器系统包括：以N个位单元的阵列中的行和列排列的存储器单元的阵列，每个字具有N位，具有位容量S的I / O总线，其是N的约数， 用于产生多个命令的模式发生器，所述命令包括命令写入命令，数据写入命令，数据读取命令和状态读取命令，所述命令写入和所述状态读取命令可被编码为S位或更少， 以及多路复用装置，用于将所选择的命令提供给I / O总线。
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