公开(公告)号：EP3404722A1

公开(公告)日：2018-11-21

申请号：EP17171514.7

申请日：2017-05-17

Applicant: NXP B.V.

Inventor： Al-Sa'di, Mahmoud Shehab Mohammad ,  Magnee, Petrus Hubertus Cornelis

IPC: H01L29/66 ,  H01L21/266 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/26513 ,  H01L21/266 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/167 ,  H01L29/36 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor switch device and a method of making the same. The method includes providing a semiconductor substrate having a major surface and a first semiconductor region having a first conductivity type. The method further includes implanting ions into the first semiconductor region through an opening in a mask positioned over the first semiconductor region, thereby to form a well region located in the first semiconductor region, the well region having a second conductivity type different to the first conductivity type. The method also includes depositing and patterning a gate electrode material on a gate dielectric to form a gate electrode located directly above the well region. The method further includes performing ion implantation to form a source region located in the well region on a first side of the gate, and to form a drain region located outside the well region on a second side of the gate.

公开(公告)号：EP3343615A2

公开(公告)日：2018-07-04

申请号：EP17203057.9

申请日：2017-11-22

Applicant: Renesas Electronics Corporation

Inventor： Kawashima, Yoshiyuki ,  Hashimoto, Takashi

IPC: H01L27/1157 ,  H01L27/11573 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L27/1157 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3418 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/28282 ,  H01L23/528 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

Abstract: A semiconductor device in which the cell size is small and disturbance in reading operation is suppressed, and a method for manufacturing the semiconductor device. A first memory cell has a first memory transistor. A second memory cell has a second memory transistor. A control gate is shared by the first memory cell and the second memory cell. In plan view, the control gate is sandwiched between a first memory gate of the first memory transistor and a second memory gate of the second memory transistor.

公开(公告)号：EP3072147A4

公开(公告)日：2017-09-13

申请号：EP13898043

申请日：2013-11-20

Applicant: INTEL CORP

Inventor： ST AMOUR ANTHONY ,  STEIGERWALD JOSEPH

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L29/78

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5283 ,  H01L23/53266 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP3203502A2

公开(公告)日：2017-08-09

申请号：EP17152904.3

申请日：2017-01-24

Applicant: Semiconductor Manufacturing International Corporation (Shanghai) ,  Semiconductor Manufacturing International Corporation (Beijing)

Inventor： HONG, Bo ,  ZHANG, Shuai

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L27/11524

CPC classification number: H01L29/66492 ,  H01L21/266 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/788 ,  H01L29/7881

Abstract: Memory cells and fabrication methods thereof are provided. An exemplary method includes providing a substrate having a well region; forming a select gate structure, a floating gate structure and a dummy gate structure on a surface of the well region; forming a first lightly doped region, a second lightly doped region and a third lightly doped region in the well region, the first lightly doped region and the second lightly doped region being at two sides of the select gate structure respectively, the second lightly doped region being in between the select gate structure and the floating gate structure, and the third lightly doped region being in between the floating gate structure and the dummy gate structure; and forming bit line region in the first lightly doped region and a source region in the third lightly doped region, the source region being enclosed by the third lightly doped region.

Abstract translation: 提供存储器单元及其制造方法。 示例性方法包括提供具有阱区的衬底; 在阱区的表面上形成选择栅极结构，浮置栅极结构和伪栅极结构; 在阱区中形成第一轻掺杂区，第二轻掺杂区和第三轻掺杂区，第一轻掺杂区和第二轻掺杂区分别位于选择栅极结构的两侧，第二轻掺杂区 位于所述选择栅极结构和所述浮栅结构之间，并且所述第三轻掺杂区位于所述浮栅结构和所述伪栅极结构之间; 以及在所述第一轻掺杂区域中形成位线区域以及在所述第三轻掺杂区域中形成源极区域，所述源极区域被所述第三轻掺杂区域包围。

公开(公告)号：EP2701196A3

公开(公告)日：2017-04-26

申请号：EP13179637.7

申请日：2013-08-07

Applicant: STMicroelectronics, Inc.

Inventor： Liu, Qing ,  Khare, Prasanna ,  Loubet, Nicolas

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/76816 ,  H01L21/823425 ,  H01L21/823864 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: A semiconductor device includes a semiconductor substrate having a channel region therein, a gate structure above the channel region, and source and drain regions on opposite sides of the gate structure. A respective contact is on each of the source and drain regions. At least one of the source and drain regions has an inclined upper contact surface with the respective contact. The inclined upper contact surface has at least a 50% greater area than would a corresponding flat contact surface.

Abstract translation: 一种半导体器件包括其中具有沟道区的半导体衬底，在沟道区上方的栅极结构以及在栅极结构的相对侧上的源极区和漏极区。 各个触点位于每个源极和漏极区域上。 源区和漏区中的至少一个具有与相应触点倾斜的上接触表面。 倾斜的上接触表面比相应的平坦接触表面具有至少大50％的面积。

公开(公告)号：EP3002780A1

公开(公告)日：2016-04-06

申请号：EP15184691.2

申请日：2015-09-10

Applicant: Renesas Electronics Corporation

Inventor： KAWASHIMA, Yoshiyuki ,  YOSHIDA, Shoji

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/30 ,  H01L29/66 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L29/7923 ,  H01L21/28176 ,  H01L21/28282 ,  H01L21/3003 ,  H01L21/324 ,  H01L27/11573 ,  H01L29/513 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor device including a nonvolatile memory cell and a field effect transistor together is improved in performance. In a method of manufacturing a semiconductor device, a hydrogen-containing insulating film is formed before heat treatment of a semiconductor wafer, the hydrogen-containing insulating film covering a gate electrode and a gate insulating film in a region that will have a memory cell therein, and exposing a region that will have therein a MISFET configuring a peripheral circuit. Consequently, hydrogen in the hydrogen-containing insulating film is diffused into an interface between the gate insulating film and the semiconductor substrate, and thereby a defect at the interface is selectively repaired.

公开(公告)号：EP1986240B1

公开(公告)日：2016-03-09

申请号：EP08162077.5

申请日：2003-10-23

Applicant: Fujitsu Semiconductor Limited

Inventor： Anezaki, Toru, Fujitsu Limited

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115 ,  H01L21/8247 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/8239 ,  H01L27/105

CPC classification number: H01L21/823462 ,  H01L21/2652 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11573 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/7881 ,  H01L29/792

Abstract: A semiconductor device is provided which has insulating film side wall spacers having a barrier function. The semiconductor device comprises: a gate oxide film and a gate electrode formed on and above a semiconductor substrate; source/drain regions formed in the semiconductor substrate; and first laminated side wall spacers having two or more layers and formed on side walls of the gate electrode, the first laminated side wall spacers including a nitride film as a layer other than an outermost layer, the outermost layer being made of an oxide film or an oxynitride film and having a bottom surface contacting the semiconductor substrate, the gate oxide film or a side wall spacer layer other than the nitride film. The semiconductor device may further comprise second laminated side wall spacers having three or more layers and formed on side walls of a laminated gate electrode structure, the second laminated side wall spacers including a nitride film as an intermediate layer not contacting the semiconductor substrate.

公开(公告)号：EP2901482A1

公开(公告)日：2015-08-05

申请号：EP13841180.6

申请日：2013-08-26

Applicant: Silicon Storage Technology Inc.

Inventor： SU, Chien-Sheng ,  TADAYONI, Mandana ,  CHEN, Yueh-Hsin

IPC: H01L29/06

CPC classification number: H01L29/66492 ,  H01L21/265 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/7833

Abstract: A transistor and method of making same include a substrate, a conductive gate over the substrate and a channel region in the substrate under the conductive gate. First and second insulating spacers are laterally adjacent to first and second sides of the conductive gate. A source region in the substrate is adjacent to but laterally spaced from the first side of the conductive gate and the first spacer, and a drain region in the substrate is adjacent to but laterally spaced apart from the second side of the conductive gate and the second spacer. First and second LD regions are in the substrate and laterally extend between the channel region and the source or drain regions respectively, each with a portion thereof not disposed under the first and second spacers nor under the conductive gate, and each with a dopant concentration less than that of the source or drain regions.

公开(公告)号：EP2894664A2

公开(公告)日：2015-07-15

申请号：EP15150714.2

申请日：2015-01-09

Applicant: Socionext Inc.

Inventor： Matsuura, Katsuyoshi ,  Ariyoshi, Junichi

IPC: H01L21/8234 ,  H01L27/02 ,  H01L21/8238 ,  H01L27/07

CPC classification number: H01L27/0288 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823814 ,  H01L27/0629 ,  H01L27/0738 ,  H01L27/11517 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor integrated circuit apparatus and a manufacturing method for the same are provided in such a manner that a leak current caused by a ballast resistor is reduced, and at the same time, the inconsistency in the leak current is reduced. The peak impurity concentration of the ballast resistors (32) is made smaller than the peak impurity concentration in the extension regions (26), and the depth of the ballast resistors (32) is made greater than the depth of the extension regions (26).

Abstract translation: 提供了一种半导体集成电路装置及其制造方法，使得由镇流电阻器引起的漏电流减小，同时泄漏电流的不一致性降低。 使镇流电阻器（32）的峰值杂质浓度小于扩展区域（26）中的峰值杂质浓度，并且使镇流电阻器（32）的深度大于延伸区域（26）的深度， 。

公开(公告)号：EP2565929A3

公开(公告)日：2014-10-08

申请号：EP12179171.9

申请日：2012-08-03

Applicant: PS4 Luxco S.a.r.l.

Inventor： Saino, Kanta

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/49 ,  H01L27/108

CPC classification number: H01L29/51 ,  H01L21/28044 ,  H01L21/823842 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/4941 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor device comprises an MIS field effect transistor including a channel region made of p-conductive silicon, a gate insulating film including a first insulating film having dielectric constant higher than dielectric constant of silicon dioxide, and a gate electrode. The gate electrode includes a first metal film formed on the gate insulating film and having a work function greater than a work function of intrinsic semiconductor silicon, and a p-conductive silicon film formed on the first metal film and in contact with the first metal film.

Abstract translation: 一种半导体器件包括MIS场效应晶体管和栅电极，所述MIS场效应晶体管包括由p型导电硅制成的沟道区，包括具有比二氧化硅的介电常数高的介电常数的第一绝缘膜的栅极绝缘膜。 栅电极包括形成在栅绝缘膜上并且具有大于本征半导体硅的功函数的功函数的第一金属膜以及形成在第一金属膜上并且与第一金属膜接触的p导电硅膜 。