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公开(公告)号：EP0550286A3
公开(公告)日：1993-11-03
申请号：EP92311898.8
申请日：1992-12-31
申请人： AMDAHL CORPORATION
CPC分类号： G06F9/4843 , G06F9/463
摘要： A multiprocessor (MP) computer sytem which allows target CPU(s) to continue processing instructions while other target CPU(s) are processing instructions of emulation code to reach their end of a Domain Unit of Operation before synchronization. A two-level MP sync is used since the target CPUs must be in between units of operation when the updates occur since a unit of operation can be one instruction or it can be many instructions that together emulate one instruction. Two level MP sync allows CPUs that are going to be serialized to continue to process single instructions (no emulation code) while other target CPUs are in emulation mode.
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公开(公告)号：EP0550285A2
公开(公告)日：1993-07-07
申请号：EP92311897.0
申请日：1992-12-31
申请人： AMDAHL CORPORATION
CPC分类号： G06F9/45558 , G06F11/0757 , G06F2009/45566
摘要： A computer system that has a machine unit of operation (MUO) used to time executions in the system, has a User State and a Control State, has multiple domains for logical processors, and and has a Domain Unit of Operation (DUO) to time domain operations in the system. The DUO is used for timing during emulation User instructions a control program in control state. The physical processor is augmented by a DUO control bit that control bit indicates that execution is within a machine unit of operation or a domain unit of operation. The DUO bit is set when a transfer is forced from User State to Control State in order to emulate a user instruction. The DUO bit can be explicitly set or reset by Control Software.
摘要翻译： 具有用于在系统中执行时间的机器操作单元（MUO）的计算机系统具有用户状态和控制状态，具有用于逻辑处理器的多个域，并且具有域操作单元（DUO）到时间 系统中的域操作。 DUO用于仿真期间的定时用户指令控制程序处于控制状态。 物理处理器由DUO控制位增强，控制位指示执行是在机器操作单元或域操作单元内。 当从用户状态到控制状态强制转移以便模拟用户指令时，DUO位置1。 控制软件可以显式设置或复位DUO位。
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公开(公告)号：EP0550290A3
公开(公告)日：1994-08-31
申请号：EP92311903.6
申请日：1992-12-31
申请人： AMDAHL CORPORATION
IPC分类号： G06F9/30
CPC分类号： G06F9/30101
摘要： A computer system having a plurality of architecturally defined separate and distinct registers formed in a common register array. The register array contains both architecturally defined general and control registers. Addressing the registers in the register array is unified whether for user or control functions.
摘要翻译： 计算机系统具有形成在公共寄存器阵列中的多个体系结构定义的分离和不同寄存器。 寄存器阵列包含架构定义的通用寄存器和控制寄存器。 无论是用户还是控制功能，寻址寄存器阵列中的寄存器都是统一的。
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公开(公告)号：EP0550285A3
公开(公告)日：1993-10-27
申请号：EP92311897.0
申请日：1992-12-31
申请人： AMDAHL CORPORATION
CPC分类号： G06F9/45558 , G06F11/0757 , G06F2009/45566
摘要： A computer system that has a machine unit of operation (MUO) used to time executions in the system, has a User State and a Control State, has multiple domains for logical processors, and and has a Domain Unit of Operation (DUO) to time domain operations in the system. The DUO is used for timing during emulation User instructions a control program in control state. The physical processor is augmented by a DUO control bit that control bit indicates that execution is within a machine unit of operation or a domain unit of operation. The DUO bit is set when a transfer is forced from User State to Control State in order to emulate a user instruction. The DUO bit can be explicitly set or reset by Control Software.
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公开(公告)号：EP0550290A2
公开(公告)日：1993-07-07
申请号：EP92311903.6
申请日：1992-12-31
申请人： AMDAHL CORPORATION
IPC分类号： G06F9/30
CPC分类号： G06F9/30101
摘要： A computer system having a plurality of architecturally defined separate and distinct registers formed in a common register array. The register array contains both architecturally defined general and control registers. Addressing the registers in the register array is unified whether for user or control functions.
摘要翻译： 一种计算机系统，其具有形成在公共寄存器阵列中的多个架构上限定的分离和不同寄存器。 寄存器阵列包含架构上定义的通用寄存器和控制寄存器。 无论是用户还是控制功能，对寄存器阵列中的寄存器进行寻址是统一的。
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6.发明公开2-Level multi-processor synchronization protocol 失效Zweistufiges Multiprozessorsynchronisierungsprotokoll。
公开(公告)号：EP0550286A2
公开(公告)日：1993-07-07
申请号：EP92311898.8
申请日：1992-12-31
申请人： AMDAHL CORPORATION
CPC分类号： G06F9/4843 , G06F9/463
摘要： A multiprocessor (MP) computer sytem which allows target CPU(s) to continue processing instructions while other target CPU(s) are processing instructions of emulation code to reach their end of a Domain Unit of Operation before synchronization. A two-level MP sync is used since the target CPUs must be in between units of operation when the updates occur since a unit of operation can be one instruction or it can be many instructions that together emulate one instruction. Two level MP sync allows CPUs that are going to be serialized to continue to process single instructions (no emulation code) while other target CPUs are in emulation mode.
摘要翻译： 多处理器（MP）计算机系统，允许目标CPU继续处理指令，而其他目标CPU正在处理仿真代码的指令，以在同步之前到达其域操作单元的结束。 使用两级MP同步，因为当更新发生时，目标CPU必须在操作单元之间，因为操作单元可以是一个指令，或者它可以是一起模拟一个指令的许多指令。 两级MP同步允许将被序列化的CPU继续处理单个指令（无仿真代码），而其他目标CPU处于仿真模式。
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