2-Level multi-processor synchronization protocol
    1.
    发明公开
    2-Level multi-processor synchronization protocol 失效
    2级多处理器同步协议

    公开(公告)号:EP0550286A3

    公开(公告)日:1993-11-03

    申请号:EP92311898.8

    申请日:1992-12-31

    IPC分类号: G06F9/46 G06F11/34 G06F9/44

    CPC分类号: G06F9/4843 G06F9/463

    摘要: A multiprocessor (MP) computer sytem which allows target CPU(s) to continue processing instructions while other target CPU(s) are processing instructions of emulation code to reach their end of a Domain Unit of Operation before synchronization. A two-level MP sync is used since the target CPUs must be in between units of operation when the updates occur since a unit of operation can be one instruction or it can be many instructions that together emulate one instruction. Two level MP sync allows CPUs that are going to be serialized to continue to process single instructions (no emulation code) while other target CPUs are in emulation mode.

    2-Level multi-processor synchronization protocol
    2.
    发明公开
    2-Level multi-processor synchronization protocol 失效
    Zweistufiges Multiprozessorsynchronisierungsprotokoll。

    公开(公告)号:EP0550286A2

    公开(公告)日:1993-07-07

    申请号:EP92311898.8

    申请日:1992-12-31

    IPC分类号: G06F9/46 G06F11/34 G06F9/44

    CPC分类号: G06F9/4843 G06F9/463

    摘要: A multiprocessor (MP) computer sytem which allows target CPU(s) to continue processing instructions while other target CPU(s) are processing instructions of emulation code to reach their end of a Domain Unit of Operation before synchronization. A two-level MP sync is used since the target CPUs must be in between units of operation when the updates occur since a unit of operation can be one instruction or it can be many instructions that together emulate one instruction. Two level MP sync allows CPUs that are going to be serialized to continue to process single instructions (no emulation code) while other target CPUs are in emulation mode.

    摘要翻译: 多处理器(MP)计算机系统,允许目标CPU继续处理指令,而其他目标CPU正在处理仿真代码的指令,以在同步之前到达其域操作单元的结束。 使用两级MP同步,因为当更新发生时,目标CPU必须在操作单元之间,因为操作单元可以是一个指令,或者它可以是一起模拟一个指令的许多指令。 两级MP同步允许将被序列化的CPU继续处理单个指令(无仿真代码),而其他目标CPU处于仿真模式。