公开(公告)号：EP0586021A1

公开(公告)日：1994-03-09

申请号：EP93202772.5

申请日：1991-01-31

Applicant: ANALOG DEVICES, INCORPORATED

Inventor： Ferguson, Paul F. Jr. ,  Adams, Robert W. ,  Ganesan, Apparajan

IPC: H03M7/32 ,  H03M3/02

CPC classification number: H03G3/02 ,  H03M3/43 ,  H03M3/446 ,  H03M3/45 ,  H03M3/454 ,  H03M7/3028 ,  H03M7/3035 ,  H03M7/304

Abstract: The invention relates to a digital noise shaper circuit for generating an output digital data stream having pre-defined noise characteristics from a multi-bit input digital data stream. The noise shaper circuit includes a greater than two-pole digital filter network (1902-1910) for receiving and processing an error signal to generate the output data stream, a comparator (1924) responsive to the output data stream for generating a feedback signal, a feedback processing network (1926-1934) responsive to the feedback signal for frequency-shaping the feedback signal, and adders (1912-1920) for digitally adding the multi-bit input digital data stream and the frequency-shaped feedback signal to generate the error signal.

Abstract translation: 本发明涉及一种用于从多位输入数字数据流产生具有预定噪声特性的输出数字数据流的数字噪声整形器电路。 噪声整形器电路包括用于接收和处理误差信号以产生输出数据流的大于两极的数字滤波器网络（1902-1910）;响应于输出数据流以产生反馈信号的比较器（1924） 响应于用于对反馈信号进行频率整形的反馈信号的反馈处理网络（1926-1934）以及用于数字相加多位输入数字数据流和频率形状的反馈信号的加法器（1912-1920），以产生 误差信号。

公开(公告)号：EP0586021B1

公开(公告)日：1996-11-27

申请号：EP93202772.5

申请日：1991-01-31

Applicant: ANALOG DEVICES, INCORPORATED

Inventor： Ferguson, Paul F. Jr. ,  Adams, Robert W. ,  Ganesan, Apparajan

IPC: H03M7/32 ,  H03M3/02

CPC classification number: H03G3/02 ,  H03M3/43 ,  H03M3/446 ,  H03M3/45 ,  H03M3/454 ,  H03M7/3028 ,  H03M7/3035 ,  H03M7/304

公开(公告)号：EP0774835A3

公开(公告)日：1997-06-25

申请号：EP97200236.4

申请日：1993-09-30

Applicant: ANALOG DEVICES, INCORPORATED

Inventor： Adams, Robert W. ,  Coln, Michael ,  Kwan, Tom W.

IPC: H03H17/06

CPC classification number: H03H17/0628

Abstract: An asynchronous digital sample rate converter includes a random access memory (100) for storing input data values, and a read only memory (104) for storing a reduced set of interpolation filter coefficients. Input data is written to the random access memory at the input sample rate. Output samples are provided from a multiply/accumulate engine which, given a stream of input data and filter coefficients, produces an output sample upon request at the output frequency. The initial address for reading input data from the random access memory, and the addresses for coefficients from the read only memory are provided by an auto-centering scheme which is a first order closed loop system with a digital integrator fed by an approximation of the input to output sample rate ratio. This auto-centering scheme may include a feed forward low pass filter to cancel steady state error, and an interpolated write address to reduce noise. A circuit determining the output to input sample rate ratios can also be provided to scale coefficient addresses and resulting output samples to allow for decimation. This circuit includes a form of digital hysteresis to eliminate noise. The ROM coefficients are reduced by relying on the symmetry of the impulse response of the interpolation filter and by utilizing a variable step size forward and backward linear interpolation.

Abstract translation: 异步数字采样率转换器包括用于存储输入数据值的随机存取存储器（100）和用于存储减小的一组内插滤波器系数的只读存储器（104）。 输入数据以输入采样率写入随机存取存储器。 输出采样由乘法/累加引擎提供，该引擎在给定输入数据和滤波器系数的流的情况下根据输出频率的请求产生输出采样。 用于从随机存取存储器读取输入数据的初始地址以及来自只读存储器的系数地址由自动对中方案提供，该自动对中方案是一阶闭环系统，其中数字积分器通过近似输入 输出采样率比率。 该自动对中方案可以包括用于抵消稳态误差的前馈低通滤波器和用于降低噪声的内插写地址。 还可以提供确定输出与输入采样率比率的电路来缩放系数地址和结果输出采样以允许抽取。 该电路包含一种消除噪声的数字滞后形式。 ROM系数通过依赖内插滤波器的脉冲响应的对称性并通过利用可变步长前向和后向线性内插来减小。

公开(公告)号：EP0774835A2

公开(公告)日：1997-05-21

申请号：EP97200236.4

申请日：1993-09-30

Applicant: ANALOG DEVICES, INCORPORATED

Inventor： Adams, Robert W. ,  Coln, Michael ,  Kwan, Tom W.

IPC: H03H17/06

CPC classification number: H03H17/0628

Abstract: An asynchronous digital sample rate converter includes a random access memory (100) for storing input data values, and a read only memory (104) for storing a reduced set of interpolation filter coefficients. Input data is written to the random access memory at the input sample rate. Output samples are provided from a multiply/accumulate engine which, given a stream of input data and filter coefficients, produces an output sample upon request at the output frequency. The initial address for reading input data from the random access memory, and the addresses for coefficients from the read only memory are provided by an auto-centering scheme which is a first order closed loop system with a digital integrator fed by an approximation of the input to output sample rate ratio. This auto-centering scheme may include a feed forward low pass filter to cancel steady state error, and an interpolated write address to reduce noise. A circuit determining the output to input sample rate ratios can also be provided to scale coefficient addresses and resulting output samples to allow for decimation. This circuit includes a form of digital hysteresis to eliminate noise. The ROM coefficients are reduced by relying on the symmetry of the impulse response of the interpolation filter and by utilizing a variable step size forward and backward linear interpolation.

Abstract translation: 异步数字采样率转换器包括用于存储输入数据值的随机存取存储器（100）和用于存储一组缩减的内插滤波器系数的只读存储器（104）。 输入数据以输入采样率写入随机存取存储器。 从乘法/累积引擎提供输出样本，给定输入数据流和滤波器系数，根据输出频率的要求产生输出采样。 用于从随机存取存储器读取输入数据的初始地址和来自只读存储器的系数的地址由自动定心方案提供，该自动定心方案是具有通过输入的近似馈送的数字积分器的一阶闭环系统 输出采样率。 该自动定心方案可以包括用于消除稳态误差的前馈低通滤波器和内插写入地址以减少噪声。 还可以提供确定输入到输入采样速率比的电路，以缩放系数地址和产生的输出采样以允许抽取。 该电路包括一种消除噪声的数字滞后形式。 通过依赖于内插滤波器的脉冲响应的对称性并通过利用可变步长前进和反向线性插值来减小ROM系数。