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公开(公告)号：EP1908172B1
公开(公告)日：2010-04-28
申请号：EP06787210.1
申请日：2006-07-13
申请人： Cirrus Logic, Inc.
发明人： MELANSON, John, L.
IPC分类号： H03M7/34
CPC分类号： H03M7/3035 , H03M7/3026 , H03M7/3028 , H03M7/304
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2.发明公开Quantizer overload prevention for feed-back type delta-sigma modulators 有权Größenwandler-ÜberlastungsverhinderungfürDelta-Sigma-Modulatoren vom Feedback-Typ
公开(公告)号：EP2221976A2
公开(公告)日：2010-08-25
申请号：EP10004438.7
申请日：2006-07-13
申请人： Cirrus Logic, Inc.
发明人： Melanson, John L.
IPC分类号： H03M7/34
CPC分类号： H03M7/3035 , H03M7/3026 , H03M7/3028 , H03M7/304
摘要： A digital signal processing system includes a delta sigma modulator that maintains a low pass output during quantizer overload prevention conditions. In at least one embodiment, the delta sigma modulator includes a quantizer overload protected delta sigma modulator with an N-order feedback-type loop filter. A quantizer of the delta sigma modulator provides feedback to at least the first two filter stages of the loop filter. The loop filter includes at least N successive filter stages and limits an output of an initial filter stage during quantizer overload prevention conditions. If limiting the output of the initial filter stage is insufficient to prevent quantizer overload, the delta sigma modulator can progressively limit an output of at least the next successive filter stage to prevent quantizer overload, where N is a positive integer greater than or equal to two (2).
摘要翻译： 数字信号处理系统包括在量化器过载保护条件期间保持低通输出的Δ-Σ调制器。 在至少一个实施例中，Δ-Σ调制器包括具有N阶反馈型环路滤波器的量化器过载保护的Δ-Σ调制器。 Δ-Σ调制器的量化器向环路滤波器的至少前两个滤波器级提供反馈。 环路滤波器包括至少N个连续滤波器级，并且在量化器过载预防条件期间限制初始滤波器级的输出。 如果限制初始滤波器级的输出不足以防止量化器过载，则Δ-Σ调制器可以逐渐限制至少下一个连续滤波器级的输出以防止量化器过载，其中N是大于或等于二的正整数 （2）。
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公开(公告)号：EP1908172A1
公开(公告)日：2008-04-09
申请号：EP06787210.1
申请日：2006-07-13
申请人： Cirrus Logic, Inc.
发明人： MELANSON, John, L.
IPC分类号： H03M7/34
CPC分类号： H03M7/3035 , H03M7/3026 , H03M7/3028 , H03M7/304
摘要： A digital signal processing system includes a delta sigma modulator that maintains a low pass output during quantizer overload prevention conditions. In at least one embodiment, the delta sigma modulator includes a quantizer overload protected delta sigma modulator with an N- order feedback-type loop filter. A quantizer of the delta sigma modulator provides feedback to at least the first two filter stages of the loop filter. The loop filter includes at least N successive filter stages and limits an output of an initial filter stage during quantizer overload prevention conditions. If limiting the output of the initial filter stage is insufficient to prevent quantizer overload, the delta sigma modulator can progressively limit an output of at least the next successive filter stage to prevent quantizer overload, where N is a positive integer greater than or equal to two (2).
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公开(公告)号：EP1618667A1
公开(公告)日：2006-01-25
申请号：EP04725134.3
申请日：2004-04-13
发明人： JANSSEN, Erwin , REEFMAN, Derk
IPC分类号： H03M3/00
CPC分类号： H03M7/3035 , H03M3/43 , H03M3/444 , H03M3/452 , H03M3/454 , H03M7/3028 , H03M7/3037 , H03M7/304
摘要： A sigma-delta modulator (SDM) including n (n≥1) integrators in series, where a first of the n integrators receiving an input signal, at least one Q device, which acts as a quantizer when an absolute value of a signal input thereto is smaller and as a gain element (either with or without offset) when the absolute value of the signal input thereto is larger, and a device for quantizing an output of the unit. The SDM may be a feed back or feed forward SDM. The SDM may include a single or multiple Q devices. The single Q device may be positioned so that the signal input to the one Q device is an output of the last integrator and the output of the one device Ql is input to the device for quantizing and/or to the n integrators. For multiple Q devices, each of the Q devices may have different parameters set to improve stability, improve SNR, and/or reduce introduction of artifacts. The SDM may be part of an analog to digital converter and/or a digital to digital converter. The SDM may process digital or analog signals, for example, a 1-bit signal.
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公开(公告)号：EP1556953A1
公开(公告)日：2005-07-27
申请号：EP03808803.5
申请日：2003-09-22
IPC分类号： H03M7/00
CPC分类号： H03M7/3035
摘要： A data converter comprises a discrete-time sigma delta modulator e.g. for driving a Class-D power amplifier. The low-pass filter of the sigma delta modulator is modified by adding a suitably positioned pole to lower the oscillation frequency (limit cycle) of the sigma delta modulator in order to obtain increased clustering of the pulses applied to the output of the data converter.
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6.发明授权
公开(公告)号：EP2221976B1
公开(公告)日：2012-12-26
申请号：EP10004438.7
申请日：2006-07-13
申请人： Cirrus Logic, Inc.
发明人： Melanson, John L.
IPC分类号： H03M7/34
CPC分类号： H03M7/3035 , H03M7/3026 , H03M7/3028 , H03M7/304
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公开(公告)号：EP1556953B1
公开(公告)日：2007-05-09
申请号：EP03808803.5
申请日：2003-09-22
IPC分类号： H03M7/00
CPC分类号： H03M7/3035
摘要： A data converter comprises a discrete-time sigma delta modulator e.g. for driving a Class-D power amplifier. The low-pass filter of the sigma delta modulator is modified by adding a suitably positioned pole to lower the oscillation frequency (limit cycle) of the sigma delta modulator in order to obtain increased clustering of the pulses applied to the output of the data converter.
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8.发明公开High speed digital delta-sigma modulator with integrated upsampler 有权Digitaler Delta-Sigma-Hochgeschwindigkekemodulator mit integriertem Upsampler
公开(公告)号：EP1753135A1
公开(公告)日：2007-02-14
申请号：EP06016142.9
申请日：2006-08-02
CPC分类号： H03H17/0657 , H03M3/508 , H03M7/3017 , H03M7/3035 , H03M7/304
摘要： Apparatus, and a related method, for converting digital signals directly to radio-frequency (RF) analog signals. The apparatus includes a single high-speed delta-sigma modulator and an integrated upsampler that increases the data rate of digital input samples by a selected factor, such as nine times. The delta-sigma modulator is configured to include a feedback multiplier coefficients that are selected to greatly facilitate operation of associated adders. At least one critical adder includes a carry-select adder modification that further speeds up the add operation and ensures that the apparatus operates at desirably high frequencies.
摘要翻译： 用于将数字信号直接转换成射频（RF）模拟信号的装置和相关方法。 该装置包括单个高速Δ-Σ调制器和集成上采样器，其通过选择的因子（例如9次）增加数字输入样本的数据速率。 Δ-Σ调制器被配置为包括被选择以极大地促进相关加法器的操作的反馈乘数系数。 至少一个关键加法器包括进位选择加法器修改，其进一步加速加法运算，并确保装置以期望的高频工作。
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公开(公告)号：EP0586021A1
公开(公告)日：1994-03-09
申请号：EP93202772.5
申请日：1991-01-31
CPC分类号： H03G3/02 , H03M3/43 , H03M3/446 , H03M3/45 , H03M3/454 , H03M7/3028 , H03M7/3035 , H03M7/304
摘要： The invention relates to a digital noise shaper circuit for generating an output digital data stream having pre-defined noise characteristics from a multi-bit input digital data stream. The noise shaper circuit includes a greater than two-pole digital filter network (1902-1910) for receiving and processing an error signal to generate the output data stream, a comparator (1924) responsive to the output data stream for generating a feedback signal, a feedback processing network (1926-1934) responsive to the feedback signal for frequency-shaping the feedback signal, and adders (1912-1920) for digitally adding the multi-bit input digital data stream and the frequency-shaped feedback signal to generate the error signal.
摘要翻译： 本发明涉及一种用于从多位输入数字数据流产生具有预定噪声特性的输出数字数据流的数字噪声整形器电路。 噪声整形器电路包括用于接收和处理误差信号以产生输出数据流的大于两极的数字滤波器网络（1902-1910）;响应于输出数据流以产生反馈信号的比较器（1924） 响应于用于对反馈信号进行频率整形的反馈信号的反馈处理网络（1926-1934）以及用于数字相加多位输入数字数据流和频率形状的反馈信号的加法器（1912-1920），以产生 误差信号。
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公开(公告)号：EP0501580A1
公开(公告)日：1992-09-02
申请号：EP92200522.8
申请日：1992-02-24
CPC分类号： H03M7/3035 , H03M3/43 , H03M3/444 , H03M3/452 , H03M7/3028 , H03M7/3037
摘要： Sigma-delta modulator comprising a low-pass filter of the Nth order, which is constituted by a series combination of N first-order integrating sections (6.1, 6.2, 6.3, ..., 6.N) comprising each an integrator (12.1, 12.2, 12.3, ..., 12.N) and a limiter (14.1, 14.2, 14.3, ..., 14.N). The individual output signals of the sections are weighted by means of corresponding weighting amplifiers (16.1, 16.2, 16.3, ..., 16.N) and added together in an adder stage (18). The gains of the sections and the limiting values of the limiters are selected so that the last limiter (14.N) in the series arrangement is activated first when the signal level in the sigma-delta modulator increases, subsequently the last-but-one limiter, and so on. This reduces the order of the filter system each time by one when there is an increasing signal level, and causes the sigma-delta modulator to remain stable.
摘要翻译： Σ-Δ调制器，包括N阶低通滤波器，它由N个一阶积分部分（6.1,6.2,6.3，...，6.N）的串联组合构成，包括每个积分器（12.1 ，12.2,12.3，...，12.N）和限制器（14.1,14.2,14.3，...，14.N）。 通过对应的加权放大器（16.1,16.2,16.3，...，16.N）对这些部分的各个输出信号进行加权，并在加法器级（18）中相加。 选择这些部分的增益和限制器的限制值，使得当Σ-Δ调制器中的信号电平增加时，串联装置中的最后限制器（14.N）首先被激活，随后是最后一个 限制器等。 当存在增加的信号电平时，这会每次减少滤波器系统的次序，并且使Σ-Δ调制器保持稳定。
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