公开(公告)号：EP1137983B1

公开(公告)日：2003-06-04

申请号：EP99964951.0

申请日：1999-10-29

申请人： ANALOG DEVICES, INCORPORATED

发明人： GARDE, Douglas ,  ZATSMAN, Alexei ,  LEZEROVITZ, Aryeh ,  GREENFIELD, Zvi ,  LEVINE, David, R. ,  FRIDMAN, Jose

IPC分类号： G06F9/315

CPC分类号： G06F9/30018 ,  G06F9/30 ,  G06F9/30032 ,  G06F9/30101

公开(公告)号：EP1163593A2

公开(公告)日：2001-12-19

申请号：EP00905689.6

申请日：2000-01-20

申请人： ANALOG DEVICES, INCORPORATED

发明人： GREENFIELD, Zvi

IPC分类号： G06F13/16

CPC分类号： G06F13/1684 ,  G06F13/1605

摘要： A CPU includes a number of functional units that cooperate together to execute instructions. On-chip memory is divided into several sections, each of which is connected to an associated internal bus. All of the functional units are connected to each of the internal busses so that each of the functional units can read from and write to all memory locations. To conduct a transaction with memory, a functional unit determines which memory location it requires, and then arbitrates for mastership of the bus associated with the section of memory containing that memory location. By providing two or more internal busses, two or more bus transactions can occur simultaneously. A virtual bus is provided to facilitate transactions between functional units. The virtual bus is a bus arbiter without an associated physical bus. To conduct a transaction with another functional unit, the functional unit arbitrates for mastership of the virtual bus, the virtual bus monitors the internal busses or communicates with the other bus arbiters to determine which of the internal busses is unoccupied and, upon receiving a request to access the virtual bus, assigns one of the internal busses to the requesting functional unit. Using a virtual bus is advantageous since requesting access to the virtual bus has the affect of arbitrating for each of the physical busses simultaneously. Thus, the amount of time spent arbitrating for access to the physical busses is minimized. Also, since the physical busses typically do not run at 100 % capacity, allocating use of the physical busses to non-memory transactions maximizes use of the physical busses without significantly distracting from the ability of the functional units to access memory. Finally, using a virtual bus instead of an additional physical bus takes up much less space than would be required if a dedicated physical bus were provided for transactions between functional units.

公开(公告)号：EP1151388A1

公开(公告)日：2001-11-07

申请号：EP00902418.3

申请日：2000-01-14

申请人： ANALOG DEVICES, INCORPORATED

发明人： KOSLAWSKY, Robert ,  GREENFIELD, Zvi ,  SANDBANK, Alberto, E.

IPC分类号： G06F13/368 ,  G11C11/406

CPC分类号： G11C11/406 ,  G06F13/368

摘要： A multiprocessor system includes a distributed bus arbitration system in which bus arbitration takes place simultaneously on each of the multiple processors connected to the bus. Each processor has a local arbitrator of common configuration with the other local arbitrators and a dedicated request line. Each local arbitrator is connected to each dedicated request line to monitor signals on lines indicative of requests for mastership of the bus by the processors. The multiprocessor system also includes a distributed DRAM refresh system in which each processor has a local DRAM refresh controller of common configuration with the other DRAM refresh controllers. Thus, as mastership of the bus passes from one processor to the other, the new bus master's local DRAM refresh controller can continue the DRAM refresh process without requiring information to be transferred from the old bus master to the new bus master, and without duplicating DRAM refresh operations.

公开(公告)号：EP1137983A2

公开(公告)日：2001-10-04

申请号：EP99964951.0

申请日：1999-10-29

申请人： ANALOG DEVICES, INCORPORATED

发明人： GARDE, Douglas ,  ZATSMAN, Alexei ,  LEZEROVITZ, Aryeh ,  GREENFIELD, Zvi ,  LEVINE, David, R. ,  FRIDMAN, Jose

IPC分类号： G06F9/315

CPC分类号： G06F9/30018 ,  G06F9/30 ,  G06F9/30032 ,  G06F9/30101

摘要： A digital signal processor includes a computation block with an arithmetic logic unit, a multiplier, a shifter and a register file. The computation block includes a plurality of registers for storing instructions and operands in a bit format as a continuous bit stream, and utilizes a bit transfer mechanism for transferring in a single cycle a bit field of an arbitrary bit length between the plurality of registers and the shifter. The plurality of registers may be general purpose registers located in the register file. The register file may further include at laest one control information register for storing control information used by the bit transfer mechanism.