公开(公告)号：EP0958717A4

公开(公告)日：2002-07-24

申请号：EP97920374

申请日：1997-04-11

Applicant: ARIZONA DIGITAL INC

Inventor： BERDING ANDREW R

IPC: H05K1/02 ,  H05K1/14 ,  H05K7/14

CPC classification number: H05K1/0248 ,  H05K1/0216 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09254 ,  H05K2201/09263

Abstract: A data processing system includes a backplane and a plurality of logic boards connected to the backplane by a plurality of connectors. In one embodiment of the invention, a set of common points (23, 24) is electrically coupled to the connectors by individual conductive traces between each common point (23) and the corresponding pins (31-36) of the connectors. The common points are preferably centrally located among the plurality of connectors to reduce propagation delay. A connector (75) can be attached at the common points. The traces are separated from each other by lateral displacement in a single plane. If the backplane is a multi-layered printed circuit board, the traces are separated from each other by vertical displacement between the layers of the printed circuit board or by both vertical and horizontal displacement. The traces to the connectors nearest the common points (83) have a minimum length (96) greater than the distance (92) between the nearest connectors and the common points.