FAULT TOLERANT ASYNCHRONOUS CIRCUITS
    1.
    发明公开
    FAULT TOLERANT ASYNCHRONOUS CIRCUITS 有权
    容许出错的异步电路

    公开(公告)号:EP2020085A2

    公开(公告)日:2009-02-04

    申请号:EP07761447.7

    申请日:2007-04-27

    IPC分类号: H03K19/003

    摘要: New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single - event effects SEE-tolerant configurations (210, 210', 301,404, 510, 520, 800) are shown and described for combinational logic circuits and state-holding logic circuits The invention further provides SEE-tolerant configurations for SRAM memory circuits (700, 800)

    CONVERSION OF A SYNCHRONOUS FPGA DESIGN INTO AN ASYNCHRONOUS FPGA DESIGN
    5.
    发明公开
    CONVERSION OF A SYNCHRONOUS FPGA DESIGN INTO AN ASYNCHRONOUS FPGA DESIGN 有权
    伊朗伊藤园电力公司的UMWANDLUNG EINES SYNCHRONEN FPGA-ENTWURF

    公开(公告)号:EP2100242A2

    公开(公告)日:2009-09-16

    申请号:EP07870125.7

    申请日:2007-12-31

    发明人: MANOHAR, Rajit

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5059

    摘要: Methods and systems for converting synchronous circuit designs to asynchronous circuit designs, and particularly programmable asynchronous circuit designs. Provide is a systematic, workable and repeatable process for evaluating synchronous circuit designs, converting the wires, switches/connections and logic functions to equivalent-function asynchronous circuit designs and hence implementing a functionally equivalent asynchronous circuit with all the benefits thereof. Further provided are a process for systematically doing the conversion and hardware equivalents (in form or functional description) for the asynchronous components. Using the present invention, any synchronous circuit design can be converted to an asynchronous equivalent, typically with no change to the original design implementation.

    摘要翻译: 描述了将同步电路设计转换为异步电路设计的方法和系统。 一种方法可以包括将同步电路设计转换为异步数据流设计。 可以确定同步电路设计的功能特性。 同步电路设计可以包括多个同步逻辑块和多个连接盒。 可以将每个同步逻辑块基于功能特性转换到对应的异步数据流逻辑块。 对应的异步数据流逻辑块可以提供可以使用协议信号的对应异步数据流逻辑功能。 每个接线盒基于功能特性,可以转换为可编程开关点和可编程开关。

    SYNCHRONOUS TO ASYNCHRONOUS LOGIC CONVERSION
    8.
    发明公开
    SYNCHRONOUS TO ASYNCHRONOUS LOGIC CONVERSION 审中-公开
    同步异步逻辑的实现IN

    公开(公告)号:EP2260419A1

    公开(公告)日:2010-12-15

    申请号:EP09709709.1

    申请日:2009-02-06

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5059

    摘要: Apparatus, systems, and methods may operate to generate a synchronous netlist from a synchronous circuit design representation, automatically substitute asynchronous components taken from an asynchronous standard cell component library for corresponding standard cell synchronous components in the synchronous netlist to form an asynchronous core, and convert the synchronous netlist to an asynchronous circuit design representation. Additional apparatus, systems, and methods are disclosed.

    SYSTEMS AND METHODS FOR PERFORMING AUTOMATED CONVERSION OF REPRESENTATIONS OF SYNCHRONOUS CIRCUIT DESIGNS TO AND FROM REPRESENTATIONS OF ASYNCHRONOUS CIRCUIT DESIGNS
    9.
    发明公开
    SYSTEMS AND METHODS FOR PERFORMING AUTOMATED CONVERSION OF REPRESENTATIONS OF SYNCHRONOUS CIRCUIT DESIGNS TO AND FROM REPRESENTATIONS OF ASYNCHRONOUS CIRCUIT DESIGNS 审中-公开
    于实现陈述同步电路的自动转换系统和方法设计了进出陈述异步电路设计

    公开(公告)号:EP2024884A2

    公开(公告)日:2009-02-18

    申请号:EP07761443.6

    申请日:2007-04-27

    发明人: MANOHAR, Rajit

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5045

    摘要: Methods (700, 800, 900) and systems (Fig. 1) automate an approach to convert a circuit design from a synchronous representation (Fig. 4A) to an asynchronous representation (Fig. 4B) without interaction or redesign. Conversion of representations of synchronous circuit designs (101) to and from representations of asynchronous circuit designs (104) enable traditional electronic design automation tools to process asynchronous designs while allowing synchronous designs to be implemented using asynchronous hardware solutions. Feedback to synchronous design tools (105) in synchronous representation enables optimization while minimizing the need for knowledge of the underlying asynchronous architecture and hardware.