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    INSTRUCTION DECODER INCLUDING TWO-WAY EMULATION CODE BRANCHING
    1.
    发明公开
    INSTRUCTION DECODER INCLUDING TWO-WAY EMULATION CODE BRANCHING 失效
    带双路口仿真代码指令译码器

    公开(公告)号：EP0853783A1

    公开(公告)日：1998-07-22

    申请号：EP96936101.0

    申请日：1996-10-04

    申请人： ADVANCED MICRO DEVICES INC.

    发明人： FAVOR, John, G.

    IPC分类号： G06F9

    CPC分类号： G06F9/382 ,  G06F9/30054 ,  G06F9/30152 ,  G06F9/30174 ,  G06F9/30185 ,  G06F9/30196 ,  G06F9/3806 ,  G06F9/3812 ,  G06F9/3816 ,  G06F9/3822 ,  G06F9/3853

    摘要： An instruction decoder (220) includes an emulation code sequencer (510) and emulation code ROM (520) for handling various instructions. The emulation code ROM includes a sequence of operations (Op) and an operation sequencing control code (OpSeq). Branch instructions such as conditional branch instructions may be encoded into the emulation code ROM so that a second branch, in combination with the branching operation controlled by the OpSeq code, is applied to an operation code sequence. Two-way branching permits flexible branching to locations within the emulation code ROM so that memory capacity is conserved. A superscalar microprocessor (120) includes an instruction decoder having an emulation code control circuit and an emulation ROM which emulates the function of a logic instruction decoder. The emulation code ROM is arranged as a matrix of multiple-operation (Op) units with each multiple-Op unit including a control field that points to a next location in the emulation code ROM. In one embodiment, the emulation code ROM is arranged to include a plurality of four-Op units, called Op quads, with each Op quad including a sequencing control field, called an OpSeq field.

    INSTRUCTION PREDECODE AND MULTIPLE INSTRUCTION DECODE
    2.
    发明授权
    INSTRUCTION PREDECODE AND MULTIPLE INSTRUCTION DECODE 失效
    BEFEHLSVORDEKODIERUNG和解码多个命令

    公开(公告)号：EP0853779B1

    公开(公告)日：2003-08-13

    申请号：EP96933144.6

    申请日：1996-10-03

    申请人： Advanced Micro Devices, Inc.

    发明人： FAVOR, John, G. ,  BEN-MEIR, Amos

    IPC分类号： G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/382 ,  G06F9/30152 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3812 ,  G06F9/3816 ,  G06F9/3822 ,  G06F9/3853

    摘要： Variable-length instructions are prepared for simultaneous decoding and execution of a plurality of instructions in parallel by predecoding each byte of an instruction, assuming each byte to be an opcode byte since the actual opcode byte is not identified. The predecoding operation associates an instruction length to each instruction byte. The instruction length is found for some instructions by reading a single instruction byte. For other instructions require more information to determine the instruction length and two or three instruction bytes are read. Based on the instruction length determination, instructions are classified into a group of instructions in which multiple instructions are decoded in parallel and a group of instructions in which multiple instructions are not decoded in parallel. Predecode information including a designation of instruction length and a designation of classification group is stored for each instruction byte. The instruction bytes and associated predecode information are applied to a decoder that includes a plurality of first group instruction decoders for decoding a plurality of parallel-decodable instructions in parallel and a second group instruction decoder for decoding instructions that are not decodable in parallel.

    INSTRUCTION PREDECODE AND MULTIPLE INSTRUCTION DECODE
    3.
    发明公开
    INSTRUCTION PREDECODE AND MULTIPLE INSTRUCTION DECODE 失效
    BEFEHLSVORDEKODIERUNG和解码多个命令

    公开(公告)号：EP0853779A1

    公开(公告)日：1998-07-22

    申请号：EP96933144.0

    申请日：1996-10-03

    申请人： Advanced Micro Devices, Inc.

    发明人： FAVOR, John, G. ,  BEN-MEIR, Amos

    IPC分类号： G06F9

    CPC分类号： G06F9/382 ,  G06F9/30152 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3812 ,  G06F9/3816 ,  G06F9/3822 ,  G06F9/3853

    摘要： Variable-length instructions are prepared for simultaneous decoding and execution of a plurality of instructions in parallel by predecoding each byte of an instruction, assuming each byte to be an opcode byte since the actual opcode byte is not identified. The predecoding operation associates an instruction length to each instruction byte. The instruction length is found for some instructions by reading a single instruction byte. For other instructions require more information to determine the instruction length and two or three instruction bytes are read. Based on the instruction length determination, instructions are classified into a group of instructions in which multiple instructions are decoded in parallel and a group of instructions in which multiple instructions are not decoded in parallel. Predecode information including a designation of instruction length and a designation of classification group is stored for each instruction byte. The instruction bytes and associated predecode information are applied to a decoder that includes a plurality of first group instruction decoders for decoding a plurality of parallel-decodable instructions in parallel and a second group instruction decoder for decoding instructions that are not decodable in parallel.

    INSTRUCTION DECODER INCLUDING TWO-WAY EMULATION CODE BRANCHING
    4.
    发明授权
    INSTRUCTION DECODER INCLUDING TWO-WAY EMULATION CODE BRANCHING 失效
    带双路口仿真代码指令译码器

    公开(公告)号：EP0853783B1

    公开(公告)日：2001-08-16

    申请号：EP96936101.3

    申请日：1996-10-04

    申请人： ADVANCED MICRO DEVICES INC.

    发明人： FAVOR, John, G.

    IPC分类号： G06F9/318 ,  G06F9/26 ,  G06F9/30

    CPC分类号： G06F9/382 ,  G06F9/30054 ,  G06F9/30152 ,  G06F9/30174 ,  G06F9/30185 ,  G06F9/30196 ,  G06F9/3806 ,  G06F9/3812 ,  G06F9/3816 ,  G06F9/3822 ,  G06F9/3853

    摘要： An instruction decoder (220) includes an emulation code sequencer (510) and emulation code ROM (520) for handling various instructions. The emulation code ROM includes a sequence of operations (Op) and an operation sequencing control code (OpSeq). Branch instructions such as conditional branch instructions may be encoded into the emulation code ROM so that a second branch, in combination with the branching operation controlled by the OpSeq code, is applied to an operation code sequence. Two-way branching permits flexible branching to locations within the emulation code ROM so that memory capacity is conserved. A superscalar microprocessor (120) includes an instruction decoder having an emulation code control circuit and an emulation ROM which emulates the function of a logic instruction decoder. The emulation code ROM is arranged as a matrix of multiple-operation (Op) units with each multiple-Op unit including a control field that points to a next location in the emulation code ROM. In one embodiment, the emulation code ROM is arranged to include a plurality of four-Op units, called Op quads, with each Op quad including a sequencing control field, called an OpSeq field.

    INSTRUCTION DECODER INCLUDING EMULATION USING INDIRECT SPECIFIERS
    5.
    发明授权
    INSTRUCTION DECODER INCLUDING EMULATION USING INDIRECT SPECIFIERS 失效
    采用仿真BY INDIREKTSPEZIFIZIERER命令解码器

    公开(公告)号：EP0853782B1

    公开(公告)日：2001-06-27

    申请号：EP96933907.6

    申请日：1996-10-04

    申请人： Advanced Micro Devices, Inc.

    发明人： FAVOR, John, G.

    IPC分类号： G06F9/318 ,  G06F9/26 ,  G06F9/30

    CPC分类号： G06F9/382 ,  G06F9/30054 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/30174 ,  G06F9/324 ,  G06F9/3812 ,  G06F9/3816 ,  G06F9/3853

    摘要： A ROM-based decoder exploits the high degree of redundancy between instructions to share various operation structures and substantially reduce memory size. The decoder includes a circuit which merges and shares common ROM sequences to reduce ROM size. A superscalar microprocessor includes an instruction decoder having an emulation code control circuit and an emulation ROM which emulates the function of a logic instruction decoder. An instruction register is loaded with a current instruction and has various bit-fields that are updated according to the state of the processor. An entry point circuit derives an emulation ROM entry point from the instruction stored in the instruction register. The emulation ROM entry point is used to address the emulation ROM, from which an operation (Op) is read. Various fields of the Op are selectively substituted from the instruction register and emulation environment registers.

    INSTRUCTION BUFFER ORGANIZATION METHOD AND SYSTEM
    9.
    发明授权
    INSTRUCTION BUFFER ORGANIZATION METHOD AND SYSTEM 失效
    命令高速缓存组织方法和系统

    公开(公告)号：EP0853781B1

    公开(公告)日：2003-08-27

    申请号：EP96935973.6

    申请日：1996-10-03

    申请人： ADVANCED MICRO DEVICES INC.

    发明人： FAVOR, John, G.

    IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38

    CPC分类号： G06F9/382 ,  G06F9/30152 ,  G06F9/30174 ,  G06F9/3806 ,  G06F9/3812 ,  G06F9/3816 ,  G06F9/3822 ,  G06F9/3853

    摘要： Variable-length instructions are prepared for simultaneous decoding and execution of a plurality of instructions in parallel by reading multiple variable-length instructions from an instruction source and determining the starting point of each instruction so that multiple instructions are presented to a decoder simultaneously for decoding in parallel. Immediately upon accessing the multiple variable-length instructions from an instruction memory, a predecoder derives predecode information for each byte of the variable-length instructions by determining an instruction length indication for that byte, assuming each byte to be an opcode byte since the actual opcode byte is not identified. The predecoder associates an instruction length to each instruction byte. The instructions and predecode information are applied to an instruction buffer circuit in a memory-aligned format. The instruction buffer circuit prepares the variable-length instructions for decoding by converting the instruction alignment from a memory alignment to an instruction alignment on the basis of the instruction length indication. The instruction buffer circuit also assists the preparation of variable-length instructions for decoding of multiple instructions in parallel by facilitating a conversion of the instruction length indication to an instruction pointer.