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    Programmable logic array integrated circuits
    3.
    发明公开
    Programmable logic array integrated circuits 失效
    用可编程逻辑阵列集成电路

    公开(公告)号：EP0746103A2

    公开(公告)日：1996-12-04

    申请号：EP96112929.3

    申请日：1993-04-07

    申请人： ALTERA CORPORATION

    发明人： Cliff, Richard G. ,  Lytle, Craig Schilling ,  Ahanin, Bahram ,  Heile, Francis B. ,  Pedersen, Bruce B. ,  Veenstra, Kerry

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/17792

    摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit.

    Programmable logic array integrated circuits
    4.
    发明公开
    Programmable logic array integrated circuits 失效
    可编程逻辑阵列集成电路

    公开(公告)号：EP0746102A2

    公开(公告)日：1996-12-04

    申请号：EP96112928.5

    申请日：1993-04-07

    申请人： ALTERA CORPORATION

    发明人： Cliff, Richard G. ,  Lytle, Craig Schilling ,  Ahanin, Bahram ,  Heile, Francis B. ,  Pedersen, Bruce B. ,  Veenstra, Kerry

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/17792

    摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit.

    摘要翻译： 可编程逻辑阵列集成电路具有多个可编程逻辑模块，这些模块在多个逻辑阵列块（“LAB”）中被组合在一起。 LAB以二维阵列排列在电路上。 提供导体网络用于将任何逻辑模块与任何其他逻辑模块互连。 另外，相邻或附近的逻辑模块可以彼此连接，以便用于例如在逻辑模块之间提供进位链和/或用于将两个或更多个模块连接在一起以提供更复杂的逻辑功能，而不必使用通用互连 网络。 提供另一种所谓的快速或通用导体网络，用于在整个电路中分配广泛使用的逻辑信号，例如时钟信号和清除信号。

    Programmable logic array integrated circuits
    6.
    发明公开
    Programmable logic array integrated circuits 失效
    Progammierbare，integrierte Logikanordnung

    公开(公告)号：EP1134896A2

    公开(公告)日：2001-09-19

    申请号：EP01112375.9

    申请日：1992-08-06

    申请人： Altera Corporation

    发明人： Pederson, Bruce B. ,  Cliff, Richard G. ,  Ahanin, Bahram ,  Lytle, Craig Schilling ,  Heile, Francis B. ,  Veenstra, Kerry Scott

    IPC分类号： H03K19/173

    CPC分类号： H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736

    摘要： A programmable logic array integrated circuit has a plurality of programmable logic elements grouped into a plurality of mutually exclusive groups. Each group includes signal conductors uniquely associated with that group for conveying signals between the programmable logic elements in that group. Other signal conductors are provided for conveying signals between the groups. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

    摘要翻译： 可编程逻辑阵列集成电路具有被分组成多个相互排斥的组的多个可编程逻辑元件。 每组包括与该组唯一相关联的信号导体，用于在该组中的可编程逻辑元件之间传送信号。 提供其他信号导体用于在组之间传送信号。 多路复用器可以以各种方式用于减少信号导体之间所需的可编程互连数量。

    Content addressable memory encoded outputs
    7.
    发明公开
    Content addressable memory encoded outputs 有权
    KodierteAusgängeeines Inhaltsadressierbaren Speichers

    公开(公告)号：EP0999554A1

    公开(公告)日：2000-05-10

    申请号：EP99308429.2

    申请日：1999-10-25

    申请人： Altera Corporation

    发明人： Heile, Francis B.

    IPC分类号： G11C15/00

    CPC分类号： G11C15/00

    摘要： In order to eliminate or substantially eliminate the need for circuitry to encode the address outputs of a content addressable memory which is equipped to perform sum-of-products logic, the memory contents are stored in such a way that the sum-of-products circuitry can encode the address outputs. A data word may be stored at several different locations in the memory, each of those locations being associated with a respective one of the positions or places in the encoded address that is to contain an affirmative response when the stored data word matches an applied data word. The sum-of-products circuitry of the memory is used to logically combine the outputs of the memory associated with each place of the encoded address in order to produce the appropriately encoded address output signal for that place.

    摘要翻译： 为了消除或基本上消除对配备为执行产品总和逻辑的内容可寻址存储器的地址输出进行编码的电路的需要，存储器内容以这样的方式存储，使得产品总和电路 可以对地址输出进行编码。 数据字可以存储在存储器中的几个不同的位置处，这些位置中的每一个与编码地址中的相应位置相关联，当存储的数据字与所应用的数据字匹配时，其包含肯定响应 。 存储器的总和电路用于逻辑地组合与编码地址的每个位置相关联的存储器的输出，以便为该位置产生适当编码的地址输出信号。

    Programmable logic architecture incorporating a content addressable embedded array block
    8.
    发明公开
    Programmable logic architecture incorporating a content addressable embedded array block 审中-公开
    可编程逻辑架构与嵌入的内容可寻址阵列块

    公开(公告)号：EP0913944A2

    公开(公告)日：1999-05-06

    申请号：EP98309004.4

    申请日：1998-11-03

    申请人： Altera Corporation

    发明人： Veenstra, Kerry ,  Heile, Francis B.

    IPC分类号： H03K19/177

    CPC分类号： H03K19/1776 ,  G11C7/1045 ,  G11C15/00 ,  H03K19/17704 ,  H03K19/17736

    摘要： The invention relates to an integrated circuit that can be configured to operate as a content addressable memory. The integrated circuit includes a first functional block that stores at least one keyword dataword which is associated with a group of associated data words. The integrated circuit also includes a second functional block that stores the group of associated datawords. The second functional block is connected to the first functional block in such a way that if a request dataword received at the first functional block matches at least one keyword dataword stored therein, then an associated result dataword included in the group of associated data words stored in the second functional block is output by the second functional block. Typically, the integrated circuit chip is a complex programmable logic device architecture (CPLD).