公开(公告)号：EP1207640A3

公开(公告)日：2005-10-19

申请号：EP01308917.2

申请日：2001-10-19

申请人： Altima Communications, Inc.

发明人： Chang, Michael ,  Sokol, Michael

IPC分类号： H04J3/06 ,  H04L12/56

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F5/065 ,  G06F2205/064 ,  H04J3/0697 ,  H04L49/103 ,  H04L49/205 ,  H04L49/254 ,  H04L49/351 ,  H04L2012/5665 ,  H04L2012/5681 ,  H04L2012/5682 ,  Y02D10/126

摘要： A system for reducing clock speed and power consumption in a network chip. The system has a core that transmits and receives signals at a first clock speed. A receive buffer is in communication with the core and configured to transmit the signals to the core at the first clock speed. A transmit buffer is in communication with the core and configured to receive signals from the core at the first clock speed. A sync is configured to receive signals in the receive buffer at a second clock speed and to transmit the signals from the transmit buffer at the second clock speed. The sync is in communication with the transmit buffer and the receive buffer.

公开(公告)号：EP1207640A2

公开(公告)日：2002-05-22

申请号：EP01308917.2

申请日：2001-10-19

申请人： Altima Communications, Inc.

发明人： Chang, Michael ,  Sokol, Michael

IPC分类号： H04J3/06 ,  H04L12/56

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F5/065 ,  G06F2205/064 ,  H04J3/0697 ,  H04L49/103 ,  H04L49/205 ,  H04L49/254 ,  H04L49/351 ,  H04L2012/5665 ,  H04L2012/5681 ,  H04L2012/5682 ,  Y02D10/126

摘要： A system for reducing clock speed and power consumption in a network chip. The system has a core that transmits and receives signals at a first clock speed. A receive buffer is in communication with the core and configured to transmit the signals to the core at the first clock speed. A transmit buffer is in communication with the core and configured to receive signals from the core at the first clock speed. A sync is configured to receive signals in the receive buffer at a second clock speed and to transmit the signals from the transmit buffer at the second clock speed. The sync is in communication with the transmit buffer and the receive buffer.

摘要翻译： 一种降低网络芯片时钟速度和功耗的系统。 该系统具有以第一时钟速度发送和接收信号的核心。 接收缓冲器与核心通信并且被配置为以第一时钟速度将信号发送到核心。 发送缓冲器与核心通信并且被配置为以第一时钟速度从核心接收信号。 同步被配置为以第二时钟速度在接收缓冲器中接收信号，并以第二时钟速度从发送缓冲器发送信号。 同步与发送缓冲器和接收缓冲器通信。