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8 条记录 (耗时 0.011 秒)

    Switch having virtual shared memory
    2.
    发明公开
    Switch having virtual shared memory 有权
    交换与虚拟共享存储器

    公开(公告)号：EP1248415A3

    公开(公告)日：2003-10-01

    申请号：EP01308479.3

    申请日：2001-10-03

    申请人： Altima Communications, Inc.

    发明人： Sokol, Michael ,  Chien,Sheng Feng (William)

    IPC分类号： H04L12/56

    CPC分类号： H04L49/45 ,  H04L49/103 ,  H04L49/351 ,  H04L49/352

    摘要： A network of switches having a first switch having a first memory interface and a first expansion port. The network also has an expansion bus having a first expansion bus interface and a second expansion bus interface. The first expansion bus interface is connected to the first expansion port. A second switch has a second memory interface and a second expansion port. The second expansion port is connected to the second expansion bus interface, thereby connecting the first switch to the second switch, wherein the expansion bus allows the first switch to directly access the second memory interface through the second switch and the second switch to directly access the first memory interface through the first switch.

    Switch having virtual shared memory
    4.
    发明公开
    Switch having virtual shared memory 有权
    Vermittlungsstelle mit virtuellem geteiltem Speicher

    公开(公告)号：EP1248415A2

    公开(公告)日：2002-10-09

    申请号：EP01308479.3

    申请日：2001-10-03

    申请人： Altima Communications, Inc.

    发明人： Sokol, Michael ,  Chien,Sheng Feng (William)

    IPC分类号： H04L12/56

    CPC分类号： H04L49/45 ,  H04L49/103 ,  H04L49/351 ,  H04L49/352

    摘要： A network of switches having a first switch having a first memory interface and a first expansion port. The network also has an expansion bus having a first expansion bus interface and a second expansion bus interface. The first expansion bus interface is connected to the first expansion port. A second switch has a second memory interface and a second expansion port. The second expansion port is connected to the second expansion bus interface, thereby connecting the first switch to the second switch, wherein the expansion bus allows the first switch to directly access the second memory interface through the second switch and the second switch to directly access the first memory interface through the first switch.

    摘要翻译： 一种交换机网络，具有具有第一存储器接口和第一扩展端口的第一开关。 该网络还具有扩展总线，其具有第一扩展总线接口和第二扩展总线接口。 第一个扩展总线接口连接到第一个扩展端口。 第二开关具有第二存储器接口和第二扩展端口。 第二扩展端口连接到第二扩展总线接口，从而将第一开关连接到第二开关，其中扩展总线允许第一开关通过第二开关直接访问第二存储器接口，而第二开关直接访问第二开关 第一个内存接口通过第一个交换机。

    Method and apparatus for reducing clock speed and power consumption
    5.
    发明公开
    Method and apparatus for reducing clock speed and power consumption 审中-公开
    Verfahren und Vorrichtung zur Verringerung der Taktgeschwindigkeit und des Leistungsverbrauches

    公开(公告)号：EP1207640A2

    公开(公告)日：2002-05-22

    申请号：EP01308917.2

    申请日：2001-10-19

    申请人： Altima Communications, Inc.

    发明人： Chang, Michael ,  Sokol, Michael

    IPC分类号： H04J3/06 ,  H04L12/56

    CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F5/065 ,  G06F2205/064 ,  H04J3/0697 ,  H04L49/103 ,  H04L49/205 ,  H04L49/254 ,  H04L49/351 ,  H04L2012/5665 ,  H04L2012/5681 ,  H04L2012/5682 ,  Y02D10/126

    摘要： A system for reducing clock speed and power consumption in a network chip. The system has a core that transmits and receives signals at a first clock speed. A receive buffer is in communication with the core and configured to transmit the signals to the core at the first clock speed. A transmit buffer is in communication with the core and configured to receive signals from the core at the first clock speed. A sync is configured to receive signals in the receive buffer at a second clock speed and to transmit the signals from the transmit buffer at the second clock speed. The sync is in communication with the transmit buffer and the receive buffer.

    摘要翻译： 一种降低网络芯片时钟速度和功耗的系统。 该系统具有以第一时钟速度发送和接收信号的核心。 接收缓冲器与核心通信并且被配置为以第一时钟速度将信号发送到核心。 发送缓冲器与核心通信并且被配置为以第一时钟速度从核心接收信号。 同步被配置为以第二时钟速度在接收缓冲器中接收信号，并以第二时钟速度从发送缓冲器发送信号。 同步与发送缓冲器和接收缓冲器通信。

    Method and apparatus of sharing an inter-chip bus for message passing and memory access
    8.
    发明公开
    Method and apparatus of sharing an inter-chip bus for message passing and memory access 有权
    用于分发芯片间总线用于消息传输和存储器访问的方法和装置

    公开(公告)号：EP1199642A2

    公开(公告)日：2002-04-24

    申请号：EP01308430.6

    申请日：2001-10-02

    申请人： Altima Communications, Inc.

    发明人： Fan, Jason ,  Sokol, Michael

    IPC分类号： G06F13/40 ,  G06F13/16

    CPC分类号： H04L12/4633 ,  G06F13/4022 ,  H04J3/062 ,  H04L47/29 ,  H04L47/30 ,  H04L47/32 ,  H04L49/103 ,  H04L49/205 ,  H04L49/254 ,  H04L49/351 ,  H04L2012/5665 ,  H04L2012/5681 ,  H04L2012/5682

    摘要： A system of switches having a memory/command bus having a first interface, a second interface and a third interface. A memory is connected to the third interface of the memory/command bus. The memory has a first memory address. A first switch monitors the memory/command bus and interprets information written to the first memory address as proxy information. The first switch is connected to the first interface of the memory/command bus. The second switch monitors the memory/command bus and interprets information written to the first memory address as proxy information. The second switch is connected to the second interface of the memory/command bus.

    摘要翻译： 具有第一接口，第二接口和第三接口的存储器/命令总线开关的系统。 存储器连接到存储器/命令总线的第三接口。 该内存具有第一内存地址。 第一开关监视存储器/命令总线并解释写入到第一存储器地址作为代理的信息。 第一开关连接到存储器/命令总线的所述第一接口。 第二开关监视存储器/命令总线并解释写入到第一存储器地址作为代理的信息。 所述第二开关被连接到存储器/命令总线的第二接口。