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    SHIFT REGISTER UNIT, GATE DRIVING CIRCUIT AND DRIVING METHOD, AND DISPLAY APPARATUS
    3.
    发明公开
    SHIFT REGISTER UNIT, GATE DRIVING CIRCUIT AND DRIVING METHOD, AND DISPLAY APPARATUS 审中-公开

    公开(公告)号：EP3411869A1

    公开(公告)日：2018-12-12

    申请号：EP16834223.6

    申请日：2016-08-12

    申请人： BOE Technology Group Co., Ltd.

    发明人： ZHENG, Haoliang ,  HAN, Seungwoo ,  YAO, Xing ,  CHOI, Hyunsic ,  SHANG, Guangliang ,  HAN, Mingfu ,  IM, Yunsik ,  JUN, Jungmok ,  DONG, Xue

    IPC分类号： G09G3/20 ,  G11C19/28

    CPC分类号： G11C19/28 ,  G09G3/20 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/184 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1251

    摘要： The present application discloses a method of driving a gate driving circuit in an operation cycle divided into a first sub-cycle and a second sub-cycle, including providing a gate driving circuit having a first plurality of shift register units with a second plurality of shift register units, the first plurality of shift register units being configured so that each odd/even numbered shift register unit includes a first bias-control terminal to receive a first/second bias signal CLK1/CLK2, a second bias-control terminal to receive a second/first bias signal CLK2/CLK1, and a first control level terminal provided with a first control voltage VC1, the second plurality of shift register units being configured so that each odd/even numbered shift register unit includes a third bias-control terminal to receive a third/fourth bias signal CLK3/CLK4, a fourth bias-control terminal to receive a fourth/third bias signal CLK4/CLK3, and a second control level terminal provided with a second control voltage VC2; configuring the first bias signal CLK1 and the second bias signal CLK2 as first pair of clock signals at respective turn-on level and turn-off level with inverted phase in the first sub-cycle; setting the first control voltage VC1 to a turn-off level so that the first plurality of shift register units is controlled along with the first pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the first sub-cycle; setting both the third bias signal CLK3 and the fourth bias signal CLK4 to a turn-off level and the second control voltage VC2 to turn-on level during the first sub-cycle; configuring the third bias signal CLK3 and the fourth bias signal CLK4 as second pair of clock signals at respective turn-on level and turn-off level with inverted phase in the second sub-cycle; setting the second control voltage VC2 to a turn-off level so that the second plurality of shift register units are controlled along with the second pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the second sub-cycle; and setting the first bias signal CLK1 and the second bias signal CLK2 to a turn-off level and the second control voltage VC1 to a turn-on level during the second sub-cycle.