公开(公告)号：EP3907759A1

公开(公告)日：2021-11-10

申请号：EP19829390.4

申请日：2019-01-04

申请人： BOE Technology Group Co., Ltd. ,  Chongqing BOE Optoelectronics Technology Co., Ltd.

发明人： XU, Zhuo ,  BAI, Yajie ,  WANG, Xiaolin ,  MA, Tongguo ,  GE, Yongli

IPC分类号： H01L23/60 ,  H01L27/12 ,  G02F1/1362

摘要： An electrostatic discharge protection circuit, a display substrate and a display apparatus are disclosed. The electrostatic discharge protection circuit includes: a first conductive portion, having an end portion; and at least one electrostatic discharge portion, arranged on a same layer as the first conductive portion and spaced from the end portion of the first conductive portion, the at least one electrostatic discharge portion being configured to discharge electrostatic charges generated at the end portion of the first conductive portion. The electrostatic discharge portion is positioned near the end portion of the first conductive portion, and the electrostatic charges accumulated at the end portion can be discharged by the electrostatic discharge portion, and thus, the electrostatic discharge portion can share a breakdown current so as to prevent static electricity from entering other effective circuits.

公开(公告)号：EP3535783A1

公开(公告)日：2019-09-11

申请号：EP16905685.0

申请日：2016-11-02

申请人： BOE Technology Group Co., Ltd. ,  Chongqing Boe Optoelectronics Technology Co., Ltd.

发明人： XU, Zhuo ,  BAI, Yajie ,  WANG, Xiaolin ,  WANG, Rui ,  SHANG, Fei ,  QIU, Haijun

IPC分类号： H01L27/12

公开(公告)号：EP3278360A1

公开(公告)日：2018-02-07

申请号：EP15851647.6

申请日：2015-09-17

申请人： BOE Technology Group Co., Ltd.

发明人： WANG, Xiaolin

IPC分类号： H01L23/60 ,  G02F1/1368

CPC分类号： H01L27/1244 ,  G02F1/136204 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136295 ,  H01L23/60 ,  H01L27/0288 ,  H01L27/0292 ,  H01L27/1259

摘要： The present disclosure provides a method for fabricating an array substrate. The method includes providing a substrate; forming a first pattern on the substrate including a plurality of signal lines and a plurality of electrostatic discharge (ESD) lines, wherein an ESD line is configured to connect two signal lines; and removing a portion of each ESD line during a process for forming a second pattern over the first pattern to disconnect the two signal lines.