ARRAY SUBSTRATE, DISPLAY PANEL AND ELECTRONIC APPARATUS

    公开(公告)号:EP4155823A1

    公开(公告)日:2023-03-29

    申请号:EP20966219.6

    申请日:2020-12-21

    IPC分类号: G03F9/00

    摘要: The embodiments of the present disclosure provide an array substrate, a display panel, and an electronic device. The array substrate includes: a base substrate; a first electrode arranged on the base substrate; a gate line arranged on the base substrate, wherein the gate line is electrically insulated from the first electrode; a second electrode arranged on a side of the gate line away from the base substrate, wherein at least one sub-pixel unit including at least one first sub-pixel unit is provided on the base substrate, and the at least one first sub-pixel unit includes: a first connection portion arranged in a same layer as the second electrode and a second connection portion arranged in a same layer as the gate line, wherein the second connection portion is electrically connected to the first electrode, and an orthographic projection of the second connection portion on the base substrate at least partially overlaps an orthographic projection of the first connection portion on the base substrate.

    THIN-FILM TRANSISTOR AND MANUFACTURING METHOD THEREFOR, AND ARRAY SUBSTRATE AND ELECTRONIC APPARATUS

    公开(公告)号:EP4053917A1

    公开(公告)日:2022-09-07

    申请号:EP21830212.3

    申请日:2021-05-27

    摘要: A thin-film transistor and a manufacturing method therefor, and an array substrate and an electronic apparatus. The thin-film transistor comprises a substrate (BS), and an active layer (ACT), which is located on the substrate (BS), wherein the active layer (ACT) comprises multiple layers of oxides (MOL), which are arranged in a stacked manner; the multiple layers of oxides (MOL) comprise a channel layer (CH), a transition layer and a first barrier layer (BR1); the channel layer (CH) is a layer having the maximum carrier mobility in the multiple layers of oxides (MOL); the channel layer (CH) is a crystalline oxide layer or an amorphous oxide layer; the transition layer is in direct contact with the channel layer (CH); the first barrier layer (BR1) is the outermost oxide layer among the multiple layers of oxides (MOL); the first barrier layer (BR1) and the transition layer are both crystalline oxide layers; the degree of crystallization of the first barrier layer (BR1) and the degree of crystallization of the transition layer are both greater than the degree of crystallization of the channel layer (CH); and the band gap of the first barrier layer (BR1) and the band gap of the transition layer are both greater than the band gap of the channel layer. The thin-film transistor has a high mobility and a high stability.

    SEMICONDUCTOR SUBSTRATE MANUFACTURING METHOD AND SEMICONDUCTOR SUBSTRATE

    公开(公告)号:EP4075516A1

    公开(公告)日:2022-10-19

    申请号:EP21830070.5

    申请日:2021-05-27

    IPC分类号: H01L29/786

    摘要: A semiconductor substrate manufacturing method and a semiconductor substrate (100). The semiconductor substrate manufacturing method comprises: when a base substrate (110) is at a first temperature, forming a first semiconductor layer (142, 142') at an interface (111, 111') on the base substrate (110), wherein the material of the first semiconductor layer (142, 142') is a first oxide semiconductor material; directly forming a second semiconductor layer (143, 143') on the first semiconductor layer (142, 142'), wherein the material of the second semiconductor layer (143, 143') is a second oxide semiconductor material; and respectively patterning the first semiconductor layer and the second semiconductor layer into a seed layer (1420, 1420') and a first channel layer (1430, 1430'), both the first channel layer (1430, 1430') and the seed layer (1420, 1420') being crystalline phase layers, wherein both the first oxide semiconductor material and the second oxide semiconductor material can be formed into crystalline phases at a second temperature, the second temperature is lower than or equal to 40 °C, and the first temperature is higher than or equal to 100 °C. Thus, phenomena such as undercutting during the subsequent etching process of an oxide semiconductor stack can be avoided.