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公开(公告)号：EP4280202A1
公开(公告)日：2023-11-22
申请号：EP22837059.9
申请日：2022-07-08
发明人： LIU, Miao , HAO, Xueguang , XU, Jingbo , YAO, Xing , WANG, Jingquan , WU, Xinyin , LI, Xinguo , WANG, Zhichong
IPC分类号： G09G3/3208 , G09G3/3266
摘要： A display substrate, comprising a base substrate (30) and a scan drive control circuit which is disposed in a non-display area of the base substrate (30). The scan drive control circuit comprises an input circuit, an output control circuit, and an output circuit. The output control circuit is connected to the input circuit and the output circuit. The output control circuit comprises a first node control capacitor and a second node control capacitor. The length of the first node control capacitor in a first direction L C1k , the length of the second node control capacitor in the first direction L C2k and the length of the scan drive control circuit in the first direction L Y satisfy (aa). L C 1 k L Y L C 2 k L Y ; L C 1 k L Y 0.20
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公开(公告)号：EP3571691A1
公开(公告)日：2019-11-27
申请号：EP17866382.9
申请日：2017-10-31
发明人： KIM, Jiha , HAN, Seungwoo , SHANG, Guangliang , ZHENG, Haoliang , YAO, Xing , WANG, Zhichong , HAN, Mingfu , YUAN, Lijun , IM, Yunsik , LV, Jing , DONG, Xue
IPC分类号： G09G3/36
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公开(公告)号：EP3951756A1
公开(公告)日：2022-02-09
申请号：EP19858715.6
申请日：2019-03-28
发明人： LIU, Peng , LIU, Bailing , LI, Fuqiang , WANG, Zhichong , FENG, Jing , LUAN, Xinglong
IPC分类号： G09G3/20
摘要： A gate driving unit, a gate driving method, a gate driving circuit, a display panel and a display device are provided. The gate driving unit includes a start terminal, a first gate driving signal output terminal, a second gate driving signal output terminal, a pull-up control node control circuit, a pull-up node control circuit, configured to control a potential of a fist pull-up node and a potential of a second pull-up node based on the potential of the pull-up control node, a first gate driving signal output circuit, a second gate driving signal output circuit, and a pull-down node control circuit, configured to control and maintain the potential of the pull-down node under the control of a third clock signal and a fourth clock signal, and control to reset the potential of the pull-down node under the control of the potential of the pull-up control node.
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4.发明公开
公开(公告)号：EP3608901A1
公开(公告)日：2020-02-12
申请号：EP17861186.9
申请日：2017-10-17
发明人： KIM, Jiha , HAN, Seung Woo , SHANG, Guangliang , YAO, Xing , ZHENG, Haoliang , HAN, Mingfu , WANG, Zhichong , YUAN, Lijun , IM, Yun Sik , LV, Jing , HUANG, Yinglong , DONG, Xue
IPC分类号： G09G3/36
摘要： A shift-buffer circuit (100), a gate driving circuit, a display panel, a display device, and a driving method. The shift-buffer circuit includes: a shift register (110) and a plurality of buffers (120) connected with the shift register (110). The shift register (110) includes a shift output terminal (SOUT); the shift register (110) is configured to output a shift output signal from the shift output terminal (SOUT), in response to a shift clock signal (CLKS); each of the buffers (120) includes a buffer input terminal (BIN) and a buffer output terminal (BOUT), the buffer input terminal (BIN) being connected with the shift output terminal (SOUT); each of the buffers (120) is configured to output a buffer output signal from the buffer output terminal (BOUT), in response to a buffer clock signal (CLKB).
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公开(公告)号：EP3779956A1
公开(公告)日：2021-02-17
申请号：EP18904492.8
申请日：2018-11-05
摘要： A shift register unit and a driving method, a grid driving circuit and a display device are disclosed. A shift register unit includes an input circuit (110), a first reset circuit (120), and an output circuit (130). The input circuit (110) includes an input terminal (INT) configured to perform a first control on the first control node (PU) and the first node (N1) in response to an input signal of the input terminal (INT), and then perform a second control, which is different from the first control, on the first node (N1) under the control of the level of the first node (N1), the first node (N1) is located in a path where the input signal incurs the first control on the first control node (PU); the first reset circuit (120) is configured to reset the first control node (PU) in response to the first reset signal; the output circuit (130) is configured to output an output signal to an output terminal (OUT) under the control of the level of the first control node (PU). The shift register unit can avoid the phenomenon of no output after switching the scanning direction due to negative bias of the threshold voltage of the transistor at the input end of the shift register unit, enhance the stability of the circuit, and have a larger threshold voltage bias margin.
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公开(公告)号：EP3686894A1
公开(公告)日：2020-07-29
申请号：EP18807544.4
申请日：2018-06-07
发明人： HAN, Mingfu , SHANG, Guangliang , HAN, Seung Woo , YAO, Xing , ZHENG, Haoliang , YUAN, Lijun , WANG, Zhichong
摘要： A shift register unit and a drive method thereof, a gate driving circuit and a display device are provided. The shift register unit (100) includes an input circuit (110), a pull-up node reset circuit (120), an output circuit (130) and a coupling circuit (140). The input circuit (110) is configured to charge a pull-up node (PU) in response to an input signal; the pull-up node reset circuit (120) is configured to reset the pull-up node (PU) in response to a reset signal; the output circuit (130) is configured to output a first clock signal to a first output terminal (OUT1) under control of a level of the pull-up node (PU); and the coupling circuit (140) is configured to control, by coupling, a potential of the pull-up node (PU) in response to a second clock signal. The shift register unit can reduce a falling edge time of the output signal of the first output terminal, thereby improving the driving capability of the shift register unit.
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