DISPLAY SUBSTRATE AND DISPLAY DEVICE
    2.
    发明公开

    公开(公告)号:EP4418273A1

    公开(公告)日:2024-08-21

    申请号:EP23818996.3

    申请日:2023-05-31

    IPC分类号: G11C19/28 G09G3/32

    摘要: The present disclosure provides a display substrate and a display device, and relates to the field of the display technology. The display substrate includes a shift register arranged on a base substrate, and the shift register includes a plurality of stages of driving circuits; a plurality of stages of the driving circuit are provided in the driving circuit area of the base substrate; a stage of driving circuit area includes a first area and a second area, and the first area is provided with a first type of transistor included in the driving circuit, a second type of transistor included in the driving circuit is provided in the second area; one side of the first area is a side of the power line away from the second area, and the other side of the first area is a side close to the second area of an active layer of the first type of transistor close to the second area; one side of the second area is a side of the power line away from the first area, and the other side of the second area is the side close to the second area of the active layer of the first type of transistor close to the second area. The present disclosure reduces the width of the driving circuit included in the display substrate along the first direction, so as to achieve the narrow frame.

    COMPENSATION METHOD AND COMPENSATION DEVICE USED FOR DISPLAY SCREEN, AND DISPLAY DEVICE

    公开(公告)号:EP3879519A1

    公开(公告)日:2021-09-15

    申请号:EP19853282.2

    申请日:2019-05-28

    IPC分类号: G09G3/36 G09G5/06

    摘要: The present disclosure provides a compensation method and compensation device for a display screen, and a display device. The compensation method includes: adjusting a charging time for a plurality of areas of the display screen so that the charging time for each area to be charged is positively related to a distance from the each area to a data voltage input terminal of the display screen; comparing a first grayscale value before compensation of a sub-pixel in an i-th row and j-th column with a second grayscale value input to a sub-pixel in an (i-1)-th row and j-th column, where i and j are both positive integers, and i>1; searching a grayscale compensation parameter corresponding to the first grayscale value and the second grayscale value from a grayscale compensation parameter table in a case where the first grayscale value is not equal to the second grayscale value; compensating the first grayscale value by the grayscale compensation parameter to obtain a third grayscale value; and inputting the third grayscale value to the sub-pixel in the i-th row and j-th column for display. In the present disclosure, it is possible to allow that the display screen when displaying an image may reach a desired target grayscale value, thereby improving the display effect.

    SHIFT REGISTER UNIT, GATE DRIVE CIRCUIT, DISPLAY DEVICE AND DRIVE METHOD

    公开(公告)号:EP3686894A1

    公开(公告)日:2020-07-29

    申请号:EP18807544.4

    申请日:2018-06-07

    IPC分类号: G11C19/28 G09G3/36

    摘要: A shift register unit and a drive method thereof, a gate driving circuit and a display device are provided. The shift register unit (100) includes an input circuit (110), a pull-up node reset circuit (120), an output circuit (130) and a coupling circuit (140). The input circuit (110) is configured to charge a pull-up node (PU) in response to an input signal; the pull-up node reset circuit (120) is configured to reset the pull-up node (PU) in response to a reset signal; the output circuit (130) is configured to output a first clock signal to a first output terminal (OUT1) under control of a level of the pull-up node (PU); and the coupling circuit (140) is configured to control, by coupling, a potential of the pull-up node (PU) in response to a second clock signal. The shift register unit can reduce a falling edge time of the output signal of the first output terminal, thereby improving the driving capability of the shift register unit.

    SHIFT REGISTER UNIT, GATE DRIVING CIRCUIT AND DRIVING METHOD, AND DISPLAY APPARATUS

    公开(公告)号:EP3411869A1

    公开(公告)日:2018-12-12

    申请号:EP16834223.6

    申请日:2016-08-12

    IPC分类号: G09G3/20 G11C19/28

    摘要: The present application discloses a method of driving a gate driving circuit in an operation cycle divided into a first sub-cycle and a second sub-cycle, including providing a gate driving circuit having a first plurality of shift register units with a second plurality of shift register units, the first plurality of shift register units being configured so that each odd/even numbered shift register unit includes a first bias-control terminal to receive a first/second bias signal CLK1/CLK2, a second bias-control terminal to receive a second/first bias signal CLK2/CLK1, and a first control level terminal provided with a first control voltage VC1, the second plurality of shift register units being configured so that each odd/even numbered shift register unit includes a third bias-control terminal to receive a third/fourth bias signal CLK3/CLK4, a fourth bias-control terminal to receive a fourth/third bias signal CLK4/CLK3, and a second control level terminal provided with a second control voltage VC2; configuring the first bias signal CLK1 and the second bias signal CLK2 as first pair of clock signals at respective turn-on level and turn-off level with inverted phase in the first sub-cycle; setting the first control voltage VC1 to a turn-off level so that the first plurality of shift register units is controlled along with the first pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the first sub-cycle; setting both the third bias signal CLK3 and the fourth bias signal CLK4 to a turn-off level and the second control voltage VC2 to turn-on level during the first sub-cycle; configuring the third bias signal CLK3 and the fourth bias signal CLK4 as second pair of clock signals at respective turn-on level and turn-off level with inverted phase in the second sub-cycle; setting the second control voltage VC2 to a turn-off level so that the second plurality of shift register units are controlled along with the second pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the second sub-cycle; and setting the first bias signal CLK1 and the second bias signal CLK2 to a turn-off level and the second control voltage VC1 to a turn-on level during the second sub-cycle.