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公开(公告)号:EP4280202A1
公开(公告)日:2023-11-22
申请号:EP22837059.9
申请日:2022-07-08
发明人: LIU, Miao , HAO, Xueguang , XU, Jingbo , YAO, Xing , WANG, Jingquan , WU, Xinyin , LI, Xinguo , WANG, Zhichong
IPC分类号: G09G3/3208 , G09G3/3266
摘要: A display substrate, comprising a base substrate (30) and a scan drive control circuit which is disposed in a non-display area of the base substrate (30). The scan drive control circuit comprises an input circuit, an output control circuit, and an output circuit. The output control circuit is connected to the input circuit and the output circuit. The output control circuit comprises a first node control capacitor and a second node control capacitor. The length of the first node control capacitor in a first direction L C1k , the length of the second node control capacitor in the first direction L C2k and the length of the scan drive control circuit in the first direction L Y satisfy (aa). L C 1 k L Y L C 2 k L Y ; L C 1 k L Y 0.20
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公开(公告)号:EP4418273A1
公开(公告)日:2024-08-21
申请号:EP23818996.3
申请日:2023-05-31
发明人: LIU, Miao , HAO, Xueguang , LIU, Libin , CHEN, Teng , WU, Xinyin , QIAO, Yong , YAO, Xing , WANG, Jingquan
摘要: The present disclosure provides a display substrate and a display device, and relates to the field of the display technology. The display substrate includes a shift register arranged on a base substrate, and the shift register includes a plurality of stages of driving circuits; a plurality of stages of the driving circuit are provided in the driving circuit area of the base substrate; a stage of driving circuit area includes a first area and a second area, and the first area is provided with a first type of transistor included in the driving circuit, a second type of transistor included in the driving circuit is provided in the second area; one side of the first area is a side of the power line away from the second area, and the other side of the first area is a side close to the second area of an active layer of the first type of transistor close to the second area; one side of the second area is a side of the power line away from the first area, and the other side of the second area is the side close to the second area of the active layer of the first type of transistor close to the second area. The present disclosure reduces the width of the driving circuit included in the display substrate along the first direction, so as to achieve the narrow frame.
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公开(公告)号:EP3571691A1
公开(公告)日:2019-11-27
申请号:EP17866382.9
申请日:2017-10-31
发明人: KIM, Jiha , HAN, Seungwoo , SHANG, Guangliang , ZHENG, Haoliang , YAO, Xing , WANG, Zhichong , HAN, Mingfu , YUAN, Lijun , IM, Yunsik , LV, Jing , DONG, Xue
IPC分类号: G09G3/36
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公开(公告)号:EP3369090A1
公开(公告)日:2018-09-05
申请号:EP16831881.4
申请日:2016-07-01
发明人: HAN, Mingfu , HAN, Seungwoo , SHANG, Guangliang , CHOI, Hyunsic , YAO, Xing , ZHENG, Haoliang , DONG, Xue , JUN, Jungmok , IM, Yunsik
IPC分类号: G09G3/36
CPC分类号: G09G3/3648 , G09G3/3677 , G09G2300/0408 , G09G2300/0426 , G09G2310/0286 , G09G2310/08 , G11C19/28
摘要: The present disclosure provides a shift register, including: an input unit, an output control unit, a first pull-down unit, a second pull-down unit, a reset unit, and a pull-down control unit. The input unit comprises a control terminal connected to a signal input terminal, a first terminal connected to a first voltage terminal, and a second terminal connected to a first node. The output control unit comprises a control terminal connected to the first node, a first terminal connected to a first clock signal terminal, and a second terminal connected to a signal output terminal. The first pull-down unit comprises a control terminal connected to a second node, a first terminal connected to the first node, and a second terminal connected to a compensation signal terminal. The second pull-down unit comprises a control terminal connected to the compensation signal terminal, and a first terminal connected to the second node.
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5.
公开(公告)号:EP3879519A1
公开(公告)日:2021-09-15
申请号:EP19853282.2
申请日:2019-05-28
发明人: YAO, Xing , HAN, Mingfu , SHANG, Guangliang , ZHU, Hao , CHU, Yifang , IM, Yunsik
摘要: The present disclosure provides a compensation method and compensation device for a display screen, and a display device. The compensation method includes: adjusting a charging time for a plurality of areas of the display screen so that the charging time for each area to be charged is positively related to a distance from the each area to a data voltage input terminal of the display screen; comparing a first grayscale value before compensation of a sub-pixel in an i-th row and j-th column with a second grayscale value input to a sub-pixel in an (i-1)-th row and j-th column, where i and j are both positive integers, and i>1; searching a grayscale compensation parameter corresponding to the first grayscale value and the second grayscale value from a grayscale compensation parameter table in a case where the first grayscale value is not equal to the second grayscale value; compensating the first grayscale value by the grayscale compensation parameter to obtain a third grayscale value; and inputting the third grayscale value to the sub-pixel in the i-th row and j-th column for display. In the present disclosure, it is possible to allow that the display screen when displaying an image may reach a desired target grayscale value, thereby improving the display effect.
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公开(公告)号:EP3369090B1
公开(公告)日:2020-05-06
申请号:EP16831881.4
申请日:2016-07-01
发明人: HAN, Mingfu , HAN, Seungwoo , SHANG, Guangliang , CHOI, Hyunsic , YAO, Xing , ZHENG, Haoliang , DONG, Xue , JUN, Jungmok , IM, Yunsik
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7.
公开(公告)号:EP3608901A1
公开(公告)日:2020-02-12
申请号:EP17861186.9
申请日:2017-10-17
发明人: KIM, Jiha , HAN, Seung Woo , SHANG, Guangliang , YAO, Xing , ZHENG, Haoliang , HAN, Mingfu , WANG, Zhichong , YUAN, Lijun , IM, Yun Sik , LV, Jing , HUANG, Yinglong , DONG, Xue
IPC分类号: G09G3/36
摘要: A shift-buffer circuit (100), a gate driving circuit, a display panel, a display device, and a driving method. The shift-buffer circuit includes: a shift register (110) and a plurality of buffers (120) connected with the shift register (110). The shift register (110) includes a shift output terminal (SOUT); the shift register (110) is configured to output a shift output signal from the shift output terminal (SOUT), in response to a shift clock signal (CLKS); each of the buffers (120) includes a buffer input terminal (BIN) and a buffer output terminal (BOUT), the buffer input terminal (BIN) being connected with the shift output terminal (SOUT); each of the buffers (120) is configured to output a buffer output signal from the buffer output terminal (BOUT), in response to a buffer clock signal (CLKB).
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公开(公告)号:EP3686894A1
公开(公告)日:2020-07-29
申请号:EP18807544.4
申请日:2018-06-07
发明人: HAN, Mingfu , SHANG, Guangliang , HAN, Seung Woo , YAO, Xing , ZHENG, Haoliang , YUAN, Lijun , WANG, Zhichong
摘要: A shift register unit and a drive method thereof, a gate driving circuit and a display device are provided. The shift register unit (100) includes an input circuit (110), a pull-up node reset circuit (120), an output circuit (130) and a coupling circuit (140). The input circuit (110) is configured to charge a pull-up node (PU) in response to an input signal; the pull-up node reset circuit (120) is configured to reset the pull-up node (PU) in response to a reset signal; the output circuit (130) is configured to output a first clock signal to a first output terminal (OUT1) under control of a level of the pull-up node (PU); and the coupling circuit (140) is configured to control, by coupling, a potential of the pull-up node (PU) in response to a second clock signal. The shift register unit can reduce a falling edge time of the output signal of the first output terminal, thereby improving the driving capability of the shift register unit.
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9.
公开(公告)号:EP3411870A1
公开(公告)日:2018-12-12
申请号:EP16852869.3
申请日:2016-11-04
发明人: SHANG, Guangliang , HAN, Seungwoo , HAN, Mingfu , ZHENG, Haoliang , YAO, Xing , CHOI, Hyunsic
IPC分类号: G09G3/20
CPC分类号: G11C19/28 , G09G3/20 , G09G3/3677 , G09G2310/0286 , G09G2310/06 , G09G2310/08 , G09G2330/06
摘要: The present application discloses a control circuit for controlling a noise reduction thin film transistor in a shift register unit. The control circuit includes a timer for initiating a timing process when the shift register is turned on, to obtain an operating time of the shift register; a threshold voltage calculator coupled to the timer for calculating a present threshold voltage based on the operating time, a gate voltage of the noise reduction thin film transistor, and an initial threshold voltage of the noise reduction thin film transistor; and a gate voltage controller coupled to the threshold voltage calculator for adjusting the gate voltage of the noise reduction thin film transistor during the noise reduction phase, to control the noise reduction thin film transistor in an ON state during the noise reduction phase.
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公开(公告)号:EP3411869A1
公开(公告)日:2018-12-12
申请号:EP16834223.6
申请日:2016-08-12
发明人: ZHENG, Haoliang , HAN, Seungwoo , YAO, Xing , CHOI, Hyunsic , SHANG, Guangliang , HAN, Mingfu , IM, Yunsik , JUN, Jungmok , DONG, Xue
CPC分类号: G11C19/28 , G09G3/20 , G09G3/3677 , G09G3/3688 , G09G2310/0267 , G09G2310/0286 , G11C19/184 , H01L27/1222 , H01L27/124 , H01L27/1251
摘要: The present application discloses a method of driving a gate driving circuit in an operation cycle divided into a first sub-cycle and a second sub-cycle, including providing a gate driving circuit having a first plurality of shift register units with a second plurality of shift register units, the first plurality of shift register units being configured so that each odd/even numbered shift register unit includes a first bias-control terminal to receive a first/second bias signal CLK1/CLK2, a second bias-control terminal to receive a second/first bias signal CLK2/CLK1, and a first control level terminal provided with a first control voltage VC1, the second plurality of shift register units being configured so that each odd/even numbered shift register unit includes a third bias-control terminal to receive a third/fourth bias signal CLK3/CLK4, a fourth bias-control terminal to receive a fourth/third bias signal CLK4/CLK3, and a second control level terminal provided with a second control voltage VC2; configuring the first bias signal CLK1 and the second bias signal CLK2 as first pair of clock signals at respective turn-on level and turn-off level with inverted phase in the first sub-cycle; setting the first control voltage VC1 to a turn-off level so that the first plurality of shift register units is controlled along with the first pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the first sub-cycle; setting both the third bias signal CLK3 and the fourth bias signal CLK4 to a turn-off level and the second control voltage VC2 to turn-on level during the first sub-cycle; configuring the third bias signal CLK3 and the fourth bias signal CLK4 as second pair of clock signals at respective turn-on level and turn-off level with inverted phase in the second sub-cycle; setting the second control voltage VC2 to a turn-off level so that the second plurality of shift register units are controlled along with the second pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the second sub-cycle; and setting the first bias signal CLK1 and the second bias signal CLK2 to a turn-off level and the second control voltage VC1 to a turn-on level during the second sub-cycle.
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