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公开(公告)号：EP0209835A3
公开(公告)日：1989-04-05
申请号：EP86109696.4
申请日：1986-07-15
发明人： Lewyn, Lanny L.
摘要： A first matrix relationship is defined by a plurality of switches operative in first and second states in accordance with the logic levels of binary signals introduced to the switches. The switches in the matrix relationship receive binary signals of relatively high binary significance. An activating line is connected to the matrix relationship to activate storage members, such as capacitors, connected to the matrix relationship. The number of storage members energized by the activating line at each instant is related to the value coded by the logic levels of the binary signals introduced to the matrix relationship. For increasing binary values, the storage members previously energized in the plurality by the activating line continue to be energized and additional storage members in the plurality are energized. An interpolating line is also provided in the first matrix relationship. The interpolating line receives a voltage related to the binary value coded by the logic levels of the binary signals of relatively low binary significance. This voltage may be produced by a second matrix relationship of conventional construction. This voltage is introduced through the interpolating line to a particular one of the storage members in the plurality, this storage member constituting the next to be connected to the activating line for increasing binary values. An output signal is produced corresponding to the cumulative value of the energy stored in the storage members in the plurality and in the particular storage member. The output signal may be produced by an integrator amplifier connected to the storage members in the plurality.
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公开(公告)号：EP0209835A2
公开(公告)日：1987-01-28
申请号：EP86109696.4
申请日：1986-07-15
发明人： Lewyn, Lanny L.
摘要： A first matrix relationship is defined by a plurality of switches operative in first and second states in accordance with the logic levels of binary signals introduced to the switches. The switches in the matrix relationship receive binary signals of relatively high binary significance. An activating line is connected to the matrix relationship to activate storage members, such as capacitors, connected to the matrix relationship. The number of storage members energized by the activating line at each instant is related to the value coded by the logic levels of the binary signals introduced to the matrix relationship. For increasing binary values, the storage members previously energized in the plurality by the activating line continue to be energized and additional storage members in the plurality are energized. An interpolating line is also provided in the first matrix relationship. The interpolating line receives a voltage related to the binary value coded by the logic levels of the binary signals of relatively low binary significance. This voltage may be produced by a second matrix relationship of conventional construction. This voltage is introduced through the interpolating line to a particular one of the storage members in the plurality, this storage member constituting the next to be connected to the activating line for increasing binary values. An output signal is produced corresponding to the cumulative value of the energy stored in the storage members in the plurality and in the particular storage member. The output signal may be produced by an integrator amplifier connected to the storage members in the plurality.
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公开(公告)号：EP0399303B1
公开(公告)日：1997-08-13
申请号：EP90108839.3
申请日：1990-05-10
发明人： Lewyn, Lanny L.
IPC分类号： H03M1/36
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公开(公告)号：EP0489412A3
公开(公告)日：1992-09-23
申请号：EP91120787.6
申请日：1991-12-03
发明人： Lewyn, Lanny L.
IPC分类号： H02M3/07
CPC分类号： H02M3/07
摘要： A positive energizing voltage, preferably in a CMOS circuit, is converted, primarily by a pair of buffer capacitors and secondarily by a filter capacitor, to a particular negative potential. One buffer capacitor is charged through first switches by the positive voltage during the positive half cycles of a clock signal. The buffer capacitor is discharged to a load during the negative half cycles of the clock signal through a circuit including such buffer capacitor, second switches, a third switch, a reference voltage (e.g. ground) line and a negative potential line. The other buffer capacitor is charged through fourth switches by the positive voltage during the negative half cycles of the clock signals. This buffer capacitor is discharged to the load during the positive half cycles of the clock signals through a circuit including such other buffer capacitor, fifth switches, the third switch, the reference voltage line and the negative potential line. The third switch has at each instant a variable state of conductivity dependent upon the magnitude of the negative potential at that instant. The magnitude of the negative potential is varied in accordance with the variations in the state of conductivity of the third switch to regulate the negative potential at a particular value. The filter capacitor is charged by the negative potential and is discharged to the load when the second and fifth switches are simultaneously open. This occurs for a brief interval every time that the polarity of the clock signal changes.
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公开(公告)号：EP0489412A2
公开(公告)日：1992-06-10
申请号：EP91120787.6
申请日：1991-12-03
发明人： Lewyn, Lanny L.
IPC分类号： H02M3/07
CPC分类号： H02M3/07
摘要： A positive energizing voltage, preferably in a CMOS circuit, is converted, primarily by a pair of buffer capacitors and secondarily by a filter capacitor, to a particular negative potential. One buffer capacitor is charged through first switches by the positive voltage during the positive half cycles of a clock signal. The buffer capacitor is discharged to a load during the negative half cycles of the clock signal through a circuit including such buffer capacitor, second switches, a third switch, a reference voltage (e.g. ground) line and a negative potential line. The other buffer capacitor is charged through fourth switches by the positive voltage during the negative half cycles of the clock signals. This buffer capacitor is discharged to the load during the positive half cycles of the clock signals through a circuit including such other buffer capacitor, fifth switches, the third switch, the reference voltage line and the negative potential line. The third switch has at each instant a variable state of conductivity dependent upon the magnitude of the negative potential at that instant. The magnitude of the negative potential is varied in accordance with the variations in the state of conductivity of the third switch to regulate the negative potential at a particular value. The filter capacitor is charged by the negative potential and is discharged to the load when the second and fifth switches are simultaneously open. This occurs for a brief interval every time that the polarity of the clock signal changes.
摘要翻译： 优选在CMOS电路中的正激励电压主要由一对缓冲电容器转换，其次由滤波电容器转换成特定的负电位。 在时钟信号的正半周期期间，通过正电压通过第一开关对一个缓冲电容器进行充电。 在包括这种缓冲电容器，第二开关，第三开关，参考电压（例如接地）线和负电位线的电路的时钟信号的负半周期期间，缓冲电容器被放电到负载。 另一个缓冲电容器在时钟信号的负半周期期间通过正电压由第四开关充电。 该缓冲电容器通过包括其他缓冲电容器，第五开关，第三开关，参考电压线和负电位线的电路在时钟信号的正半周期期间向负载放电。 第三个开关在每个瞬间具有可变的导电状态，这取决于该时刻的负电位的大小。 负电位的大小根据第三开关的导电性的变化而变化，以调节特定值的负电位。 滤波电容器由负电位充电，当第二和第五开关同时断开时，滤波电容器被放电到负载。 每当时钟信号的极性发生变化时，会发生短暂的间隔。
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公开(公告)号：EP0355835A3
公开(公告)日：1992-03-25
申请号：EP89115645.7
申请日：1989-08-24
发明人： Lewyn, Lanny L. , Lou, Perry W.
CPC分类号： H03K3/356104 , H03M1/125 , H03M1/365
摘要： A substantially constant current is divided between two lines in accordance with the relative values of an input voltage and a reference voltage respectively introduced to such lines. The currents through the first and second lines respectively charge first and second capacitances. The charges in the first and second capacitances respectively control the magnitudes of the currents flowing through first and second control members to charge the first and second capacitances. The control members are interconnected so that any difference between the flow of current through the control members and the associated capacitances becomes magnified. When the charge in an individual one of the capacitances reaches a particular value, a signal on an output terminal associated with the other capacitance changes from the first magnitude to a second magnitude. During this time, the signal associated with the first capacitance remains at substantially the first magnitude. A plurality of stages, including the comparators disccussed above, compare the input voltage with progressive values of the reference voltage. Such stages are connected to successive pairs of comparators to indicate, on the basis of the relative magnitudes of the voltages on the output terminals of such comparators, whether the reference voltage is greater than the input voltage for both comparators in such pairs. An output signal is produced by the plurality only when one pair of comparators provides an output indicating that the input voltage is between the reference voltages connected to that pair of comparators.
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公开(公告)号：EP0399303A3
公开(公告)日：1993-04-21
申请号：EP90108839.3
申请日：1990-05-10
发明人： Lewyn, Lanny L.
IPC分类号： H03M1/36
摘要： A first film disposed in a first direction on an integrated circuit chip and having uniformly spaced taps provides progressively increasing resistance values. A second film disposed on the chip in a direction opposite to the first direction at a position displaced in any direction from the first film may have a construction corresponding to that of the first film. First and second reference voltages may be respectively applied to the first and second ends of the first and second films. Particular taps on the first film may be connected to taps in corresponding positions on the second film with corresponding voltages. A plurality of differential comparators are provided, each with a signal input and a reference input. Each comparator reference input is connected to an individual one of the taps on the first film, but not necessarily to successive taps. The reference input connections to the taps may have a non-linear (e.g. a luminance) spacing in the first direction to provide a non-linear voltage (e.g. a luminance) relationship between such taps. For low voltages, however, the reference input connections to the taps may have a linear spacing in the first direction to provide a linear voltage relationship between such taps. An input voltage is applied to the signal input of all of the comparators. Binary signals representative of the input voltage are produced by the comparator in which the input voltage is substantially equal to the reference input voltage introduced to such comparator.
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9.发明公开Self-timing analog-to-digital converting system 失效系统zur Analog / Digitalwandlung mit Selbsttaktierung。
公开(公告)号：EP0355835A2
公开(公告)日：1990-02-28
申请号：EP89115645.7
申请日：1989-08-24
发明人： Lewyn, Lanny L. , Lou, Perry W.
CPC分类号： H03K3/356104 , H03M1/125 , H03M1/365
摘要： A substantially constant current is divided between two lines in accordance with the relative values of an input voltage and a reference voltage respectively introduced to such lines. The currents through the first and second lines respectively charge first and second capacitances. The charges in the first and second capacitances respectively control the magnitudes of the currents flowing through first and second control members to charge the first and second capacitances. The control members are interconnected so that any difference between the flow of current through the control members and the associated capacitances becomes magnified. When the charge in an individual one of the capacitances reaches a particular value, a signal on an output terminal associated with the other capacitance changes from the first magnitude to a second magnitude. During this time, the signal associated with the first capacitance remains at substantially the first magnitude. A plurality of stages, including the comparators disccussed above, compare the input voltage with progressive values of the reference voltage. Such stages are connected to successive pairs of comparators to indicate, on the basis of the relative magnitudes of the voltages on the output terminals of such comparators, whether the reference voltage is greater than the input voltage for both comparators in such pairs. An output signal is produced by the plurality only when one pair of comparators provides an output indicating that the input voltage is between the reference voltages connected to that pair of comparators.
摘要翻译： 根据分别引入到这些线路的输入电压和参考电压的相对值，在两条线之间划分基本恒定的电流。 通过第一和第二线的电流分别对第一和第二电容充电。 第一和第二电容中的电荷分别控制流过第一和第二控制构件的电流的大小，以对第一和第二电容充电。 控制构件相互连接，使得通过控制构件的电流流动和相关联的电容之间的任何差异被放大。 当单个电容中的电荷达到特定值时，与另一电容相关联的输出端上的信号从第一幅度变化到第二幅度。 在此期间，与第一电容相关联的信号保持基本上为第一大小。 包括上面讨论的比较器的多个级将输入电压与参考电压的渐进值进行比较。 这些级连接到连续的比较器对，以基于这些比较器的输出端上的电压的相对幅度来指示参考电压是否大于两对比较器的输入电压。 仅当一对比较器提供指示输入电压在与该对比较器之间连接的参考电压之间时，由多个输出信号产生输出信号。
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10.发明公开Networks used in A/D and D/A converters with correction for differential errors 失效在A / D-和D / A-Umsetzern verwendete Netzwerke mit Korrektur von differentiellen Fehlern。
公开(公告)号：EP0259566A2
公开(公告)日：1988-03-16
申请号：EP87110020.2
申请日：1987-07-10
发明人： Lewyn, Lanny L.
IPC分类号： H03M1/06
摘要： A digital-to-analog converter includes a decoding network and a plurality of output members such as capacitors. The decoding network receives a plurality of binary signals individually having logic levels respectively coding for binary "1" and binary "0" and individually coding for a binary value of an individually weighted significance and cumulatively coding for an analog value. The network decodes the logic levels of the binary signals and activates output members in accordance with such decoding. As the analog value coded by the logic levels of the binary signals increases, the output members previously activated in the plurality remain activated and other output members in the plurality become activated. The decoding network and the output members are disposed on an integrated circuit chip. Dependent upon their positioning on the chip, the output members have different characteristics which cause errors to be produced in the analog signal, particularly at low analog values. This invention compensates for such errors. The invention includes a second converter disposed on the chip with a construction substantially identical to the first converter and rotated on the chip substantially 180° relative to the first converter. In this way, pairs of output members of the same binary significance may have, on the average, a median position in a first direction. Individual ones of the output members in the second plurality may have the same positioning, in a second direction co-ordinate with the first direction, as corresponding ones of the output members in the first plurality.
摘要翻译： 数模转换器包括解码网络和诸如电容器的多个输出构件。 解码网络接收分别具有分别编码二进制“1”和二进制“0”的逻辑电平的多个二进制信号，并分别编码单独加权的有效值的二进制值并累加地编码模拟值。 网络解码二进制信号的逻辑电平，并根据这种解码激活输出成员。 随着由二进制信号的逻辑电平编码的模拟值增加，先前在多个激活的输出部件保持激活，并且多个其他输出部件被激活。 解码网络和输出部件设置在集成电路芯片上。 取决于它们在芯片上的定位，输出构件具有不同的特性，这导致在模拟信号中产生误差，特别是在低模拟值时。 本发明补偿了这种错误。 本发明包括设置在芯片上的第二转换器，其具有与第一转换器基本相同的结构，并相对于第一转换器在芯片上大致180度地转动。 以这种方式，具有相同二进制含义的输出成员对平均可以具有第一方向上的中位数。 第二多个输出构件中的各个可以具有与第一方向相协调的第二方向上相同的定位，作为第一多个输出构件中的相应输出构件。
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