利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

13 条记录 (耗时 0.011 秒)

    System and method for programmably adjusting gain and frequency response in a 10-gigabit ethernet/fibre channel system
    2.
    发明公开
    System and method for programmably adjusting gain and frequency response in a 10-gigabit ethernet/fibre channel system 有权
    装置和方法用于在系统10千兆位以太网/光纤通道增益和频率响应的可编程调整

    公开(公告)号：EP1388959A3

    公开(公告)日：2005-06-08

    申请号：EP03018062.4

    申请日：2003-08-07

    申请人： Broadcom Corporation

    发明人： Fujimori, Ichiro ,  Tonietto, Davide

    IPC分类号： H04B10/17

    CPC分类号： H04B10/291

    摘要： Aspects of the invention may provide a method and system for adjusting a gain and/or a frequency response of an input signal for a multimode PHY device. A signal divider (704) may apportion the input signal into a gain adjustment signal and/or an equalization adjustment signal upon receipt of the input signal. A signal adjuster (702) coupled to the signal divider (704) may adjust a gain of the apportioned gain adjustment signal within the multimode PHY device (130). An equalizer (706) coupled to the signal divider (704) may be configured to equalize the equalization adjustment signal within the multimode PHY device (130). A summer (708) coupled to the equalizer (706) and signal adjuster (702) may be adapted to sum the adjusted adjustment signal and the equalized equalization adjustment signal within the multimode PHY device (130) to create an output equalized signal (712) having a desired gain and/or frequency response.

    System and method for implementing a single chip having a multiple sub-layer PHY
    3.
    发明公开
    System and method for implementing a single chip having a multiple sub-layer PHY 审中-公开
    系统和方法，用于实现在单个芯片具有多PHY子层

    公开(公告)号：EP1388977A3

    公开(公告)日：2004-04-28

    申请号：EP03017848.7

    申请日：2003-08-05

    申请人： Broadcom Corporation

    发明人： Fujimori, Ichiro ,  Hoang, Tuan ,  Tan, Ben ,  Longo, Lorenzo

    IPC分类号： H04L12/413 ,  H04L29/06

    CPC分类号： H04B1/40 ,  H04L49/352 ,  H04L49/357

    摘要： A system and method are disclosed for supporting 10 Gigabit digital serial communications. Many of the functional components and sublayers of a 10 Gigabit digital serial communications transceiver module are integrated into a single IC chip using the same CMOS technology throughout the single chip. The single chip includes a PMD transmit/receive CMOS sublayer, a PMD PCS CMOS sublayer, a XGXS PCS CMOS sublayer, and a XAUI transmit/receive CMOS sublayer. The single chip supports both 10 Gigabit Ethernet operation and 10 Gigabit Fibre Channel operation. The single chip interfaces to a MAC, an optical PMD, and non-volatile memory.

    System and method to reduce noise in a substrate
    4.
    发明公开
    System and method to reduce noise in a substrate 有权
    System and Methode zur Verminderung vonStörsignalenin einem Substrat

    公开(公告)号：EP1388895A2

    公开(公告)日：2004-02-11

    申请号：EP03018063.2

    申请日：2003-08-07

    申请人： Broadcom Corporation

    发明人： Fujimori, Ichiro

    IPC分类号： H01L27/02

    CPC分类号： H01L27/0928 ,  H01L21/761 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092 ,  Y10S438/914

    摘要： A system and method for reducing noise in a substrate of a chip is provided. The system may include a substrate (70) doped with a first dopant. A first well (80) may be disposed on the substrate and doped with a second dopant. A second well (120) may be disposed within the first well (80) and doped with the second kind of dopant. A first transistor (100) may include one or more first transistor components disposed in the second well (120). The first transistor (100) may be adapted to employ a first type of channel having a quiet voltage source (140) connected to a body thereof. A third well (110) may be disposed within the first well (80) and doped with the first kind of dopant. A second transistor (90) may include one or more second transistor components that may be disposed in the third well (110). The second transistor (90)may be adapted to employ a second type of channel. The first well (80) may shield the substrate (70) from noise in the second well (120) and third well (110).

    摘要翻译： 提供了用于降低芯片的基板中的噪声的系统和方法。 该系统可以包括掺杂有第一掺杂剂的衬底（70）。 第一阱（80）可以设置在衬底上并掺杂有第二掺杂剂。 第二阱（120）可以设置在第一阱（80）内并掺杂第二种掺杂剂。 第一晶体管（100）可以包括设置在第二阱（120）中的一个或多个第一晶体管组件。 第一晶体管（100）可以适于采用具有连接到其本体的静电压源（140）的第一类型的沟道。 第三阱（110）可以设置在第一阱（80）内并掺杂第一种掺杂剂。 第二晶体管（90）可以包括可设置在第三阱（110）中的一个或多个第二晶体管组件。 第二晶体管（90）可以适于采用第二类型的通道。 第一阱（80）可以屏蔽衬底（70）免于第二阱（120）和第三阱（110）中的噪声。

    System and method to reduce noise in a substrate
    6.
    发明公开
    System and method to reduce noise in a substrate 有权
    系统和方法，用于在衬底中降低噪声

    公开(公告)号：EP1388895A3

    公开(公告)日：2005-08-17

    申请号：EP03018063.2

    申请日：2003-08-07

    申请人： Broadcom Corporation

    发明人： Fujimori, Ichiro

    IPC分类号： H01L27/02 ,  H01L27/092

    CPC分类号： H01L27/0928 ,  H01L21/761 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092 ,  Y10S438/914

    摘要： A system and method for reducing noise in a substrate of a chip is provided. The system may include a substrate (70) doped with a first dopant. A first well (80) may be disposed on the substrate and doped with a second dopant. A second well (120) may be disposed within the first well (80) and doped with the second kind of dopant. A first transistor (100) may include one or more first transistor components disposed in the second well (120). The first transistor (100) may be adapted to employ a first type of channel having a quiet voltage source (140) connected to a body thereof. A third well (110) may be disposed within the first well (80) and doped with the first kind of dopant. A second transistor (90) may include one or more second transistor components that may be disposed in the third well (110). The second transistor (90)may be adapted to employ a second type of channel. The first well (80) may shield the substrate (70) from noise in the second well (120) and third well (110).

    System and method for programmably adjusting gain and frequency response in a 10-gigabit ethernet/fibre channel system
    7.
    发明公开
    System and method for programmably adjusting gain and frequency response in a 10-gigabit ethernet/fibre channel system 有权
    装置和方法用于在系统10千兆位以太网/光纤通道增益和频率响应的可编程调整

    公开(公告)号：EP1388959A2

    公开(公告)日：2004-02-11

    申请号：EP03018062.4

    申请日：2003-08-07

    申请人： Broadcom Corporation

    发明人： Fujimori, Ichiro ,  Tonietto, Davide

    IPC分类号： H04B10/17

    CPC分类号： H04B10/291

    摘要： Aspects of the invention may provide a method and system for adjusting a gain and/or a frequency response of an input signal for a multimode PHY device. A signal divider (704) may apportion the input signal into a gain adjustment signal and/or an equalization adjustment signal upon receipt of the input signal. A signal adjuster (702) coupled to the signal divider (704) may adjust a gain of the apportioned gain adjustment signal within the multimode PHY device (130). An equalizer (706) coupled to the signal divider (704) may be configured to equalize the equalization adjustment signal within the multimode PHY device (130). A summer (708) coupled to the equalizer (706) and signal adjuster (702) may be adapted to sum the adjusted adjustment signal and the equalized equalization adjustment signal within the multimode PHY device (130) to create an output equalized signal (712) having a desired gain and/or frequency response.

    摘要翻译： 本发明的方面可提供用于调整增益和/或输入信号的一个多模式PHY装置的频率响应的方法和系统。 信号分频器（704）可以分配所述输入信号划分在接收到所述输入信号的增益调整信号和/或均衡调整信号。 耦合到所述信号分频器（704）的信号调节器（702）可以调节多模PHY设备（130）内的分配增益调节信号的增益。 除法器在均衡器（706）耦合到所述信号（704）可以被配置以均衡多模PHY设备（130）内的均衡调整信号。 耦合到均衡器（706）和信号调节器（702）加法器（708）可以被angepasst总结经调整的调整信号和所述多模PHY设备（130）内的均衡均衡调整信号以产生在输出均衡的信号（712） 具有所期望的增益和/或频率响应。

    Current-controlled CMOS circuit using higher voltage supply in low voltage CMOS process
    8.
    发明公开
    Current-controlled CMOS circuit using higher voltage supply in low voltage CMOS process 有权
    电流控制的CMOS电路，带有在CMOS工艺中产生的低电压增大的电源电压

    公开(公告)号：EP1394947A3

    公开(公告)日：2006-11-08

    申请号：EP03019260.3

    申请日：2003-08-26

    申请人： Broadcom Corporation

    发明人： Fujimori, Ichiro ,  Yin, Guangmin ,  Hairapetian, Armond

    IPC分类号： H03K19/0944

    CPC分类号： H03K3/3562 ,  H03K3/356043 ,  H03K17/693 ,  H03K19/09432 ,  H03K19/215

    摘要： Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C 3 MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C 3 MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C 3 MOS logic with low power conventional CMOS logic. The combined C 3 MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C 3 MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.

    System and method for implementing a single chip having a multiple sub-layer PHY
    10.
    发明公开
    System and method for implementing a single chip having a multiple sub-layer PHY 审中-公开
    用于实现具有多个子层PHY的单个芯片的系统和方法

    公开(公告)号：EP1388977A2

    公开(公告)日：2004-02-11

    申请号：EP03017848.7

    申请日：2003-08-05

    申请人： Broadcom Corporation

    发明人： Fujimori, Ichiro ,  Hoang, Tuan ,  Tan, Ben ,  Longo, Lorenzo

    IPC分类号： H04L12/413 ,  H04L29/08 ,  H01L21/28

    CPC分类号： H04B1/40 ,  H04L49/352 ,  H04L49/357

    摘要： A system and method are disclosed for supporting 10 Gigabit digital serial communications. Many of the functional components and sublayers of a 10 Gigabit digital serial communications transceiver module are integrated into a single IC chip using the same CMOS technology throughout the single chip. The single chip includes a PMD transmit/receive CMOS sublayer, a PMD PCS CMOS sublayer, a XGXS PCS CMOS sublayer, and a XAUI transmit/receive CMOS sublayer. The single chip supports both 10 Gigabit Ethernet operation and 10 Gigabit Fibre Channel operation. The single chip interfaces to a MAC, an optical PMD, and non-volatile memory.

    摘要翻译： 公开了一种用于支持10千兆位数字串行通信的系统和方法。 万兆数字串行通信收发器模块的许多功能组件和子层在整个单芯片中使用相同的CMOS技术集成到单个IC芯片中。 单芯片包括PMD发射/接收CMOS子层，PMD PCS CMOS子层，XGXS PCS CMOS子层和XAUI发射/接收CMOS子层。 该单芯片支持10千兆位以太网操作和10千兆位光纤通道操作。 单芯片接口到MAC，光学PMD和非易失性存储器。