A low voltage differential to single-ended converter
    2.
    发明公开
    A low voltage differential to single-ended converter 有权
    Niederspannungskonverter mit Differenzeingang und einem einzigen Ausgang

    公开(公告)号:EP1251640A2

    公开(公告)日:2002-10-23

    申请号:EP02252681.8

    申请日:2002-04-16

    发明人: Kocaman, Namik

    IPC分类号: H03K19/0185

    摘要: Method and circuitry for converting a differential logic signal to a single-ended logic signal eliminate slower PMOS transistors and speed up the conversion process. In specific embodiments differential logic signals of the type employed in, for example, current-controlled complementary metal-oxide-semiconductor (C3MOS) logic are converted to single-ended rail-to-rail CMOS logic levels using a differential pair of NMOS transistors with resistors as load devices and an NMOS current source transistor that provides dynamically adjusted tail current.

    摘要翻译: 用于将差分逻辑信号转换为单端逻辑信号的方法和电路消除了较慢的PMOS晶体管并加速了转换过程。 在具体实施例中,在例如电流控制的互补金属氧化物半导体(C3MOS)逻辑中使用的类型的差分逻辑信号被转换为单端轨至轨CMOS逻辑电平,使用具有 电阻作为负载器件和NMOS电流源晶体管,提供动态调整的尾电流。

    Variable gain amplifier and method for achieving variable gain amplification with high bandwidth and linearity
    4.
    发明公开
    Variable gain amplifier and method for achieving variable gain amplification with high bandwidth and linearity 审中-公开
    可变增益放大器,实现可变增益放大器具有高带宽和线性的方法

    公开(公告)号:EP1976113A2

    公开(公告)日:2008-10-01

    申请号:EP07010403.9

    申请日:2007-05-24

    发明人: Kocaman, Namik

    IPC分类号: H03G3/30

    CPC分类号: H03G3/3084 H03G1/0088

    摘要: A fine granularity, wide-range variable gain amplifier ("VGA") comprises an attenuator, a high gain signal path, a low gain signal path and a gain adjustment control to adjust a gain of the VGA, wherein the gain adjustment control is configured to cause a selective activation of at least a portion of the low gain signal path or the high gain signal path to achieve a desired overall gain.

    摘要翻译: 精细粒度,宽范围可变增益放大器(“VGA”)衰减器包括,一个高增益信号路径,低增益信号路径和增益调节控制来调节VGA的增益,worin增益调整控制被配置成 以使所述低增益信号路径或以实现所需的总体增益的高增益信号路径的至少一部分的选择性激活。

    Automatic gain control using multi-comparators
    5.
    发明公开
    Automatic gain control using multi-comparators 有权
    AutomatischeVerstärkungsregelungmit mehreren Komparatorschaltungen

    公开(公告)号:EP1727279A1

    公开(公告)日:2006-11-29

    申请号:EP05026025.6

    申请日:2005-11-29

    IPC分类号: H03G3/30 H03G3/00

    摘要: A method and apparatus for an automatic gain control (AGC) loop that utilizes multiple comparators to provide constant bandwidth tracking and step response, as well as fine granularity for decision directed convergence. In one embodiment, an odd number of comparators is used with square-law scaling at the output to achieve constant bandwidth step response for a wide range of input amplitude changes.

    摘要翻译: 一种用于自动增益控制(AGC)环路的方法和装置,其利用多个比较器来提供恒定的带宽跟踪和阶跃响应,以及用于决策定向收敛的细粒度。 在一个实施例中,使用奇数比较器,在输出处使用平方律缩放,以实现宽范围的输入幅度变化的恒定带宽阶跃响应。

    Method and Apparatus for Reference-Less Repeater with Digital Control
    6.
    发明公开
    Method and Apparatus for Reference-Less Repeater with Digital Control 有权
    用于与数字控制非参考放大器的方法和装置

    公开(公告)号:EP2897319A1

    公开(公告)日:2015-07-22

    申请号:EP14004398.5

    申请日:2014-12-23

    IPC分类号: H04L7/033

    CPC分类号: H03K5/26 H04B7/155 H04L7/033

    摘要: A frequency estimation circuit for a reference-less repeater circuit comprises an edge detector configured to measure time periods between edge-to-edge transitions in a data stream within a predetermined time interval, resulting in a plurality of edge-to-edge time periods; and a processor configured to categorize the plurality of edge-to-edge time periods into a plurality of representative groups, each representative group having a representative time period that is an integer multiple of a sampling unit time period; to determine a number of virtual transitions in the predetermined time interval based on the categorized plurality of edge-to-edge time periods and to determine a frequency estimate of the data stream based on the number of virtual transitions in the predetermined time interval.

    High Bandwidth equalizer and limiting amplifier
    7.
    发明公开
    High Bandwidth equalizer and limiting amplifier 审中-公开
    Ent。her her her her。。。。。。。。。。。

    公开(公告)号:EP2696511A1

    公开(公告)日:2014-02-12

    申请号:EP13003596.7

    申请日:2013-07-17

    IPC分类号: H04B3/04 H04B3/14 H04L25/03

    摘要: Embodiments of the present disclosure enable bandwidth extension of receiver front-end circuits without the use of inductors. As a result, significantly smaller and cheaper receiver implementations are made possible. In an embodiment, bandwidth extension is achieved by virtue of very small floating capacitors that are coupled around amplifier stages of the receiver front-end circuit. Each of the capacitors is configured to generate a negative capacitance for the preceding stage (e.g., equalizer or amplifier), thus extending the bandwidth of the preceding stage. A capacitively-degenerated crosscoupled transistor pair allows bandwidth extension for the final (e.g., amplifier) stage. Embodiments further enable DC offset compensation with the use of a digital feedback loop. The feedback loop can thus be turned on/off as needed, reducing power consumption.

    摘要翻译: 本公开的实施例使得接收机前端电路的带宽扩展不使用电感器。 因此,可以实现显着更小和更便宜的接收机实现。 在一个实施例中,通过在接收器前端电路的放大器级耦合的非常小的浮动电容器来实现带宽扩展。 每个电容器被配置为为前一级(例如,均衡器或放大器)产生负电容,从而延长前一级的带宽。 电容退化的交叉耦合晶体管对允许最终(例如,放大器)级的带宽扩展。 实施例还可以使用数字反馈回路实现DC偏移补偿。 因此,可以根据需要打开/关闭反馈回路,从而降低功耗。

    A low voltage differential to single-ended converter
    9.
    发明公开
    A low voltage differential to single-ended converter 有权
    具有差分输入和单个输出的低电压转换器

    公开(公告)号:EP1251640A3

    公开(公告)日:2003-08-27

    申请号:EP02252681.8

    申请日:2002-04-16

    发明人: Kocaman, Namik

    摘要: Method and circuitry for converting a differential logic signal to a single-ended logic signal eliminate slower PMOS transistors and speed up the conversion process. In specific embodiments differential logic signals of the type employed in, for example, current-controlled complementary metal-oxide-semiconductor (C3MOS) logic are converted to single-ended rail-to-rail CMOS logic levels using a differential pair of NMOS transistors (M1,M2) with resistors (R1,R2) as load devices and an NMOS current source transistor (M3) that provides dynamically adjusted tail current.