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公开(公告)号：EP0858210A1
公开(公告)日：1998-08-12
申请号：EP98200137.2
申请日：1991-03-05
IPC分类号： H04N1/46
摘要： An image processing apparatus comprising binarization means for converting a multi-level color signal into binary form, removal means for removing edge component from the multi-level color signal, based on a binary color signal from said binarization means, and encoder means for encoding the binary color signal from said binarization means and the multi-level color signal having edge component removed with said removal means.
摘要翻译： 一种图像处理装置，包括：二值化装置，用于将多级彩色信号转换为二进制形式;基于来自所述二值化装置的二进制彩色信号，从多级彩色信号中去除边缘分量的去除装置;以及编码装置， 来自所述二值化装置的二进制彩色信号和具有用所述去除装置去除边缘分量的多级彩色信号。
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公开(公告)号：EP0357388A3
公开(公告)日：1991-11-06
申请号：EP89308749.4
申请日：1989-08-30
发明人： Kato, Shigeo , Yasuda, Yasuhiko , Ohsawa, Hidefumi
IPC分类号： H04N1/417
CPC分类号： G06T9/004 , H04N1/4172
摘要： In an image encoding method in which a pixel of interest is predicted with reference to a plurality of pixels near the pixel of interest to be encoded, and encoding is performed on the basis of coincidence/noncoincidence between the predicted pixel and the pixel of interest, a parameter for predicting a pixel is changed on the basis of a rate of coincidence/noncoincidence of the predicted pixel and the pixel of interest.
摘要翻译： 在参考在待编码的感兴趣像素附近的多个像素来预测感兴趣像素并且基于预测像素和感兴趣像素之间的一致/不一致来执行编码的图像编码方法中， 基于预测像素和感兴趣像素的一致/不一致来改变用于预测像素的参数。
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公开(公告)号：EP0357388A2
公开(公告)日：1990-03-07
申请号：EP89308749.4
申请日：1989-08-30
发明人： Kato, Shigeo , Yasuda, Yasuhiko , Ohsawa, Hidefumi
IPC分类号： H04N1/417
CPC分类号： G06T9/004 , H04N1/4172
摘要： In an image encoding method in which a pixel of interest is predicted with reference to a plurality of pixels near the pixel of interest to be encoded, and encoding is performed on the basis of coincidence/noncoincidence between the predicted pixel and the pixel of interest, a parameter for predicting a pixel is changed on the basis of a rate of coincidence/noncoincidence of the predicted pixel and the pixel of interest.
摘要翻译： 在其中参照要编码的感兴趣像素附近的多个像素预测感兴趣像素并且基于预测像素和感兴趣像素之间的重合/不一致来执行编码的图像编码方法中， 基于预测像素和感兴趣像素的一致/不一致的速度来改变用于预测像素的参数。
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公开(公告)号：EP0234809A2
公开(公告)日：1987-09-02
申请号：EP87301187.8
申请日：1987-02-11
IPC分类号： H04N1/40
CPC分类号： H04N1/4056 , F02B2075/027 , H04N1/40062 , H04N1/40075 , H04N1/407
摘要： An image processing apparatus includes a digital data output device (1, 2) for outputting bi-level image data, a bi-level processor (4) for converting the bi-level image data into multi-level (eg 8-bit) image data, a multi-level processor (4) for performing spatial filter processing with respect to the multi-level image data output from the bi-level processor, and a PWM circuit (5) for processing the multi-level image data output from the multi-level processor using a pattern signal of a predetermined cycle and generating a PWM signal.
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公开(公告)号：EP0357388B1
公开(公告)日：1997-10-22
申请号：EP89308749.4
申请日：1989-08-30
发明人： Kato, Shigeo , Yasuda, Yasuhiko , Ohsawa, Hidefumi
IPC分类号： H04N1/417
CPC分类号： G06T9/004 , H04N1/4172
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公开(公告)号：EP0357386B1
公开(公告)日：1994-04-27
申请号：EP89308747.8
申请日：1989-08-30
发明人： Kato, Shigeo , Yasuda, Yasuhiko , Ohsawa, Hidefumi
IPC分类号： H04N1/411
CPC分类号： G06T3/4007 , H04N1/411 , H04N1/4172
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公开(公告)号：EP0357386A3
公开(公告)日：1991-05-29
申请号：EP89308747.8
申请日：1989-08-30
发明人： Kato, Shigeo , Yasuda, Yasuhiko , Ohsawa, Hidefumi
IPC分类号： H04N1/411
CPC分类号： G06T3/4007 , H04N1/411 , H04N1/4172
摘要： An image encoding apparatus includes a smoothing circuit (11) for smoothing a binary image to be encoded, a binary-encoding circuit (12) for binary-encoding the image smoothed by the smoothing circuit, a sampling circuit (13) for sub-sampling the image binary-encoded by the binary-encoding circuit, and an encoding circuit (26) for encoding the binary image sub-sampled by the sampling circuit. A degree of smoothness (G) of an image by the smoothing circuit and a threshold value (T₁) for a binary-encoding operation of the binary-encoding circuit can be varied.
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公开(公告)号：EP0234809A3
公开(公告)日：1989-03-29
申请号：EP87301187.8
申请日：1987-02-11
IPC分类号： H04N1/40
CPC分类号： H04N1/4056 , F02B2075/027 , H04N1/40062 , H04N1/40075 , H04N1/407
摘要： An image processing apparatus includes a digital data output device (1, 2) for outputting bi-level image data, a bi-level processor (4) for converting the bi-level image data into multi-level (eg 8-bit) image data, a multi-level processor (4) for performing spatial filter processing with respect to the multi-level image data output from the bi-level processor, and a PWM circuit (5) for processing the multi-level image data output from the multi-level processor using a pattern signal of a predetermined cycle and generating a PWM signal.
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公开(公告)号：EP0720379B1
公开(公告)日：2003-10-29
申请号：EP95309449.7
申请日：1995-12-27
发明人： Ohsawa, Hidefumi
CPC分类号： H04N19/593 , H04N19/13 , H04N19/146 , H04N19/149 , H04N19/176 , H04N19/60 , H04N19/91
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