公开(公告)号：EP1129415A1

公开(公告)日：2001-09-05

申请号：EP98944472.4

申请日：1998-08-21

申请人： CREDENCE SYSTEMS CORPORATION

发明人： LEPEJIAN, Yervant, David ,  MARANDJIAN, Hrant ,  GHUKASYAN, Hovhannes ,  KRAUS, Lawrence

IPC分类号： G06F17/00

CPC分类号： G11C29/12 ,  G01R31/318385 ,  G01R31/3185

摘要： A method and apparatus are provided for automatically generating the design of a BIST for embedded memories (117) of an IC. The approach relies on counters or pseudo-random generators for the implementation of many of the functions. The invention incorporates soft ware that generates equations (114) that can be used as inputs to a logic synthesis tool (116). The output of the synthesis tool feeds an automatic routing tool where it is merged with the output of the synthesis of the other portions of the integrated circuit, IC. The routing tool places and routes the signals through the logic described by the synthesis tool along with the remainder of the IC. The result is a completed IC design that includes efficient memory BIST circuitry.

公开(公告)号：EP1129415B1

公开(公告)日：2004-09-29

申请号：EP98944472.4

申请日：1998-08-21

申请人： CREDENCE SYSTEMS CORPORATION

发明人： LEPEJIAN, Yervant, David ,  MARANDJIAN, Hrant ,  GHUKASYAN, Hovhannes ,  KRAUS, Lawrence

IPC分类号： G06F17/00 ,  G11C29/00

CPC分类号： G11C29/12 ,  G01R31/318385 ,  G01R31/3185

摘要： A method and apparatus are provided for automatically generating the design of a BIST for embedded memories (117) of an IC. The approach relies on counters or pseudo-random generators for the implementation of many of the functions. The invention incorporates soft ware that generates equations (114) that can be used as inputs to a logic synthesis tool (116). The output of the synthesis tool feeds an automatic routing tool where it is merged with the output of the synthesis of the other portions of the integrated circuit, IC. The routing tool places and routes the signals through the logic described by the synthesis tool along with the remainder of the IC. The result is a completed IC design that includes efficient memory BIST circuitry.

公开(公告)号：EP1105876A1

公开(公告)日：2001-06-13

申请号：EP98945762.7

申请日：1998-08-21

申请人： CREDENCE SYSTEMS CORPORATION

发明人： LEPEJIAN,Y.D.,c/o Credence Systems Corp., ,  MARANDJIAN, Hrant ,  GHUKASYAN, Hovhannes ,  KRAUS, Lawrence

IPC分类号： G11C7/00

CPC分类号： G11C29/18

摘要： A BIST function is provided in which both the row address (50) and the column address (40) of a memory (90) to be tested may be selected independently. The present invention provides flexibility in selecting address to be tested, improves transition time between rows, and allows determination of which memory address passes or fails the test.