公开(公告)号：EP0384569A2

公开(公告)日：1990-08-29

申请号：EP90300600.5

申请日：1990-01-19

申请人： Compaq Computer Corporation

发明人： Abdoo, David G. ,  Mayer, Dale J.

IPC分类号： G06F12/06

CPC分类号： G06F12/0676

摘要： An adder (204,206,208) and a comparator (242) form portions of a modular memory address block determination circuit. The starting address of the first block and the enable signal of the first block are added to produce the starting address of the second block. This procedure is repeated for each block. The determined starting address for each block is compared with the requested memory address and, unless the block is inhibited or disabled, if equal a signal indicates a match. The circuit is used on a circuit board which emulates three conventionally separate memory circuit boards. The registers for each emulated circuit board are provided and appropriate bus signals are developed.

摘要翻译： 加法器（204,206,208）和比较器（242）形成模块存储器地址块确定电路的部分。 第一块的起始地址和第一块的使能信号被相加以产生第二块的起始地址。 对每个块重复该过程。 将确定的每个块的起始地址与请求的存储器地址进行比较，并且除非块被禁止或禁用，否则等于一个信号指示匹配。 该电路用于模拟三个常规分离的存储器电路板的电路板上。 提供每个仿真电路板的寄存器，开发合适的总线信号。

公开(公告)号：EP0384569B1

公开(公告)日：1996-06-12

申请号：EP90300600.5

申请日：1990-01-19

申请人： Compaq Computer Corporation

发明人： Abdoo, David G. ,  Mayer, Dale J.

IPC分类号： G06F12/06

CPC分类号： G06F12/0676

公开(公告)号：EP0384569A3

公开(公告)日：1991-10-23

申请号：EP90300600.5

申请日：1990-01-19

申请人： Compaq Computer Corporation

发明人： Abdoo, David G. ,  Mayer, Dale J.

IPC分类号： G06F12/06

CPC分类号： G06F12/0676

摘要： An adder (204,206,208) and a comparator (242) form portions of a modular memory address block determination circuit. The starting address of the first block and the enable signal of the first block are added to produce the starting address of the second block. This procedure is repeated for each block. The determined starting address for each block is compared with the requested memory address and, unless the block is inhibited or disabled, if equal a signal indicates a match. The circuit is used on a circuit board which emulates three conventionally separate memory circuit boards. The registers for each emulated circuit board are provided and appropriate bus signals are developed.

公开(公告)号：EP0493001B1

公开(公告)日：1996-09-11

申请号：EP91311830.3

申请日：1991-12-19

申请人： Compaq Computer Corporation

发明人： Tran, Thahn T. ,  Abdoo, David G.

IPC分类号： G06F1/10 ,  H03K12/00

CPC分类号： H03K5/15026 ,  G06F1/10

公开(公告)号：EP0493001A3

公开(公告)日：1992-10-21

申请号：EP91311830.3

申请日：1991-12-19

申请人： Compaq Computer Corporation

发明人： Tran, Thahn T. ,  Abdoo, David G.

IPC分类号： G06F1/10 ,  H03K12/00

CPC分类号： H03K5/15026 ,  G06F1/10

摘要： A clock buffer circuit (10) for a computer system, and a computer system incorporating the same, are disclosed. The clock buffer circuit includes a differential input buffer (14) for receiving the input clock signal, with its output coupled to the input of a phase locked loop (PLL) (20). The switching level of the differential input buffer is adjustable (18), either by adjusting the DC bias applied to the input clock signal, or by adjusting the reference signal, which changes the point in the cycle of the input clock signal at which the differential buffer switches. The PLL synchronizes its output to an edge of the output of the differential buffer, but maintains the same duty cycle (e.g., 50%). Accordingly, the clock buffer circuit may have its delay adjusted, by modifying a voltage divider, applying a variable voltage, or programmably via a digital-to-analog converter, to match the delays of other clock buffer circuits in the computer system, reducing the clock skew in the system. A sine wave may be used as the input clock signal, so that harmonic noise is reduced in the system.

公开(公告)号：EP0493001A2

公开(公告)日：1992-07-01

申请号：EP91311830.3

申请日：1991-12-19

申请人： Compaq Computer Corporation

发明人： Tran, Thahn T. ,  Abdoo, David G.

IPC分类号： G06F1/10 ,  H03K12/00

CPC分类号： H03K5/15026 ,  G06F1/10

摘要： A clock buffer circuit (10) for a computer system, and a computer system incorporating the same, are disclosed. The clock buffer circuit includes a differential input buffer (14) for receiving the input clock signal, with its output coupled to the input of a phase locked loop (PLL) (20). The switching level of the differential input buffer is adjustable (18), either by adjusting the DC bias applied to the input clock signal, or by adjusting the reference signal, which changes the point in the cycle of the input clock signal at which the differential buffer switches. The PLL synchronizes its output to an edge of the output of the differential buffer, but maintains the same duty cycle (e.g., 50%). Accordingly, the clock buffer circuit may have its delay adjusted, by modifying a voltage divider, applying a variable voltage, or programmably via a digital-to-analog converter, to match the delays of other clock buffer circuits in the computer system, reducing the clock skew in the system. A sine wave may be used as the input clock signal, so that harmonic noise is reduced in the system.

摘要翻译： 公开了一种用于计算机系统的时钟缓冲电路（10）以及包含该计算机系统的计算机系统。 时钟缓冲电路包括用于接收输入时钟信号的差分输入缓冲器（14），其输出耦合到锁相环（PLL）（20）的输入端。 差分输入缓冲器的开关电平可调（18），通过调整施加到输入时钟信号的直流偏置，或通过调整参考信号，该参考信号改变输入时钟信号的周期中的点，其中差分 缓冲开关 PLL将其输出同步到差分缓冲器输出的边沿，但保持相同的占空比（例如，50％）。 因此，时钟缓冲器电路可以通过修改分压器，施加可变电压或经由数模转换器可编程地调整其延迟，以匹配计算机系统中的其它时钟缓冲器电路的延迟，从而减少 系统中的时钟偏移。 可以使用正弦波作为输入时钟信号，从而在系统中降低谐波噪声。