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    Method and apparatus for distributing interrupts in a scalable symmetric multiprocessor system without changing the bus width or bus protocol
    1.
    发明公开
    Method and apparatus for distributing interrupts in a scalable symmetric multiprocessor system without changing the bus width or bus protocol 失效
    改变的方法和装置，用于中断在一个可扩展的对称多处理器系统分布，而不总线宽度或总线协议

    公开(公告)号：EP0827085A3

    公开(公告)日：1999-02-03

    申请号：EP97306157.5

    申请日：1997-08-13

    申请人： Compaq Computer Corporation

    发明人： Mayer, Dale J. ,  Olarig, Sompong P. ,  Whiteman, William F. ,  Heinrich, David F.

    IPC分类号： G06F13/24

    CPC分类号： G06F13/24

    摘要： A method for supporting multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, includes the steps of assigning a unique identification number to each bus agent, receiving bus requests from the bus agents over four data lines in groups of four, and granting bus ownership to a selected one of the requesting bus agents. Similarly, a computer system that supports multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, includes structure for assigning a unique identification number to each bus agent, four data lines for receiving bus requests from the bus agents in groups of four, and structure for granting bus ownership to a selected one of the requesting bus agents.

    Memory block address determination circuit
    2.
    发明公开
    Memory block address determination circuit 失效
    Speicherblockadressenermittlungsschaltkreis。

    公开(公告)号：EP0384569A2

    公开(公告)日：1990-08-29

    申请号：EP90300600.5

    申请日：1990-01-19

    申请人： Compaq Computer Corporation

    发明人： Abdoo, David G. ,  Mayer, Dale J.

    IPC分类号： G06F12/06

    CPC分类号： G06F12/0676

    摘要： An adder (204,206,208) and a comparator (242) form portions of a modular memory address block determination circuit. The starting address of the first block and the enable signal of the first block are added to produce the starting address of the second block. This procedure is repeated for each block. The determined starting address for each block is compared with the requested memory address and, unless the block is inhibited or disabled, if equal a signal indicates a match. The circuit is used on a circuit board which emulates three conventionally separate memory circuit boards. The registers for each emulated circuit board are provided and appropriate bus signals are developed.

    摘要翻译： 加法器（204,206,208）和比较器（242）形成模块存储器地址块确定电路的部分。 第一块的起始地址和第一块的使能信号被相加以产生第二块的起始地址。 对每个块重复该过程。 将确定的每个块的起始地址与请求的存储器地址进行比较，并且除非块被禁止或禁用，否则等于一个信号指示匹配。 该电路用于模拟三个常规分离的存储器电路板的电路板上。 提供每个仿真电路板的寄存器，开发合适的总线信号。

    Method and system for performing concurrent read and write cycles in a network switch
    6.
    发明公开
    Method and system for performing concurrent read and write cycles in a network switch 失效
    方法和系统，用于在网络交换结构同时执行读和写周期

    公开(公告)号：EP0854612A3

    公开(公告)日：1999-06-16

    申请号：EP97310662.8

    申请日：1997-12-30

    申请人： Compaq Computer Corporation

    发明人： Walker, William J. ,  Kotzur, Gary B. ,  Hareski, Patricia E. ,  Witkowski, Michael L. ,  Mayer, Dale J.

    IPC分类号： H04L12/44 ,  H04L29/04 ,  H04L12/40 ,  H04L12/56

    CPC分类号： H04L49/351 ,  H04L49/254 ,  H04L49/354

    摘要： A system for performing concurrent read and write cycles in a network switch. The network switch includes several network ports, a data bus and a switch manager to execute a concurrent read and write cycle on the data bus by asserting a first port number to identify a source port followed by a second port number to identify a destination port. Each of the ports includes a network interface for sending and receiving data packets and a data interface to store the first port number, to assert data received from the network interface onto the data bus if that port is identified by the first port number, and to retrieve data from the data bus for transmission by the network interface if that port is identified by the second port number. In this manner, data is transferred directly between a source and a destination port without being buffered in the switch manager. The bandwidth of the data bus is increased since data is transferred only once on the data bus. Latches are provided for the ports to latch the read port number to allow that write port number to be asserted during the cycle. A method of executing a concurrent read and write cycle includes the steps of asserting a first port number to identify a source port, latching the first port number, asserting a second port number to identify a destination port, and concurrently writing and reading the data on the data bus.

    Method and apparatus for distributing interrupts in a symmetric multiprocessor system
    7.
    发明公开
    Method and apparatus for distributing interrupts in a symmetric multiprocessor system 失效
    一种用于在对称多处理器系统中断分配的方法和装置

    公开(公告)号：EP0827084A3

    公开(公告)日：1999-02-03

    申请号：EP97306156.7

    申请日：1997-08-13

    申请人： Compaq Computer Corporation

    发明人： Olarig, Sompong P. ,  Mayer, Dale J. ,  Whiteman, William F.

    IPC分类号： G06F13/24

    CPC分类号： G06F13/24

    摘要： A distributed interrupt controller system for use in a multiprocessor environment, has at least two local programmable interrupt controllers (LOPICs) coupled to at least one central programmable interrupt controller (COPIC) via a dedicated bus. The COPIC functions as a master arbiter, while the LOPICs, each of which may be integrated with its corresponding processing unit, and any other non-master COPICs are treated as bus agents. Bus grant is achieved by a "round robin" arbitration protocol. For distributed delivery of interrupts, the master arbiter compares a current-task-priority-register value associated with each bus agent to determine the agent that is least busy for delivery of the interrupt thereto.

    Network switch with statistics read accesses
    8.
    发明公开
    Network switch with statistics read accesses 失效
    Netzwerkkoppelfeld mit Lesezugriffen auf Statistiken

    公开(公告)号：EP0854606A2

    公开(公告)日：1998-07-22

    申请号：EP97310652.9

    申请日：1997-12-30

    申请人： Compaq Computer Corporation

    发明人： Hareski, Patricia E. ,  Walker, William J. ,  Kotzur, Gary B. ,  Mayer, Dale J. ,  Witkowski, Michael L.

    IPC分类号： H04L12/24 ,  H04L12/44 ,  H04L12/40 ,  H04L12/56

    CPC分类号： H04L41/26 ,  H04L41/046 ,  H04L41/24 ,  H04L49/201 ,  H04L49/351 ,  H04L49/354

    摘要： A network switch including a plurality of network ports for receiving and transmitting data, where each port includes at least one statistics register for storing statistics information, such as Ethernet statistical and configuration information. The switch also includes a switch manager, which further includes a memory, retrieval logic for detecting a statistics request signal and for respondingly retrieving the statistics information for storage in the memory, and response logic for asserting a statistics response signal after the statistics information is stored. A processor is coupled to the switch manager through a bus, where the processor asserts the statistics request signal and then detects assertion of the statistics response signal. Upon detecting the response signal, the processor retrieves the statistics information from the memory. In this manner, the processor is removed from direct connection to the statistics registers and free to complete other tasks while the information is being gathered by the switch manager, thereby increasing the efficiency of the processor and of the network switch. Each port preferably includes a network interface, a processor port interface for enabling the switch manager to retrieve the statistical information, and a data bus interface for network traffic. The switch manager thus includes two separate bus connections to each of the ports, so that statistical reads do not interfere with network data packet flow.

    摘要翻译： 一种网络交换机，包括用于接收和发送数据的多个网络端口，其中每个端口包括至少一个用于存储诸如以太网统计信息和配置信息的统计信息的统计寄存器。 交换机还包括开关管理器，其还包括存储器，用于检测统计信号请求信号的检索逻辑和用于响应地检索用于存储在存储器中的统计信息，以及用于在存储统计信息之后断言统计响应信号的响应逻辑 。 处理器通过总线耦合到交换机管理器，其中处理器断言统计请求信号，然后检测统计响应信号的断言。 在检测到响应信号时，处理器从存储器检索统计信息。 以这种方式，处理器从直接连接到统计寄存器被移除，并且在交换管理器收集信息的同时可以自由地完成其他任务，从而提高处理器和网络交换机的效率。 每个端口优选地包括网络接口，用于使交换机管理器能够检索统计信息的处理器端口接口和用于网络业务的数据总线接口。 因此，交换管理器包括到每个端口的两个单独的总线连接，使得统计读取不会干扰网络数据分组流。

    Data destination facility
    9.
    发明公开
    Data destination facility 失效
    数据目的地设施

    公开(公告)号：EP0426386A3

    公开(公告)日：1992-11-25

    申请号：EP90311749.7

    申请日：1990-10-26

    申请人： Compaq Computer Corporation

    发明人： Thayer, John S. ,  Mayer, Dale J. ,  Landry, John A. ,  Izquierdo, Javier F. ,  Culley, Paul R.

    IPC分类号： G06F13/16 ,  G06F12/06

    CPC分类号： G06F12/0653

    摘要： A memory mapping and module enabling circuit for allowing logical 128 kbyte memory blocks to be defined for any location in any module (58) connected to a memory system. A RAM (126) is addressed by the system address lines defining 128 kbyte blocks, with the output data (TA, RASEN*) providing the row address strobe enable signals for a particular memory module and the address values necessary to place the 128 kbyte block within the module (58). Various other parameters such as write protect status (HWP) and memory location (HLOCMEM*) are also provided by the RAM. Circuits and techniques for programming and reading the RAM are provided.