公开(公告)号：EP0428917A2

公开(公告)日：1991-05-29

申请号：EP90120911.4

申请日：1990-10-31

Applicant: Compaq Computer Corporation

Inventor： Hamid, Mustafa Ali ,  Thoma III, Roy E. ,  Thayer, John S.

IPC: G06F12/08

CPC classification number: G06F13/4243 ,  G06F12/0888

Abstract: A method for slowing down a high speed microprocessor with an internal cache to maintain compatibility with application software written for slower speed microprocessors. The internal cache of the processor is invalidated during the slowdown and the cache address comparison circuitry is directed to evaluate external addresses for a preset interval, preventing the processor from the accessing the cache, thereby slowing down the processor. The external address evaluation direction is released when a bus requesting device indicates a bus request during the slowdown, allowing the processor to respond to the bus request promptly to prevent possible latency problems from occurring, but still maintaining the processor in a halted state.

Abstract translation: 一种使用内部缓存降低高速微处理器的方法，以保持与为较慢速度微处理器编写的应用软件的兼容性。 处理器的内部高速缓存在减速期间无效，并且缓存地址比较电路用于以预设间隔评估外部地址，防止处理器访问高速缓存，从而减慢处理器的速度。 当总线请求设备在减速期间指示总线请求时，外部地址评估方向被释放，允许处理器迅速地响应总线请求，以防止发生可能的等待时间问题，但仍然使处理器处于停止状态。

公开(公告)号：EP0519740A3

公开(公告)日：1993-02-24

申请号：EP92305658.4

申请日：1992-06-19

Applicant: Compaq Computer Corporation

Inventor： Abernathy, Michael G. ,  Fletcher, Angie M. ,  Santeler, Paul ,  Thoma III, Roy E.

IPC: H05K1/00 ,  G06F1/16

CPC classification number: H05K1/0216 ,  H05K1/0237 ,  H05K2201/09254 ,  H05K2201/10689 ,  Y10T307/492

Abstract: An electrical system wherein the electrical conductive traces on the circuit boards are routed to achieve a balanced net to reduce noise caused by transmission line reflections. A trace (202,216,248,274) is routed from the source terminal (200,214,236,260) of the net to a balanced junction (204,218,238,288) wherein if there are an odd number of load terminals, or loads, the balanced junction is located at one of the loads (204,238). The remaining loads are grouped into branches wherein each branch includes an equal number of loads. A trace is routed between each of the loads of each branch to serially connect the loads of each branch together, or, a trace is routed from a center one of the branch loads to each of the remaining branch loads, forming subbranches. In an alternate embodiment, a balanced subbranch is developed. The balanced load is connected to a pseudo-balanced load, which further receives an equal number of branches. The 3 pseudo-balanced load is then connected to another pseudo-balanced load, which may also receive an equal number of branches. This pseudo-balanced load is connected to the source. In another alternative, two balanced subbranches have their balanced loads connected to a central balanced load. This balanced load may receive even further numbers of equal branches. The balanced load is connected to the source.

公开(公告)号：EP0519740A2

公开(公告)日：1992-12-23

申请号：EP92305658.4

申请日：1992-06-19

Applicant: Compaq Computer Corporation

Inventor： Abernathy, Michael G. ,  Fletcher, Angie M. ,  Santeler, Paul ,  Thoma III, Roy E.

IPC: H05K1/00 ,  G06F1/16

CPC classification number: H05K1/0216 ,  H05K1/0237 ,  H05K2201/09254 ,  H05K2201/10689 ,  Y10T307/492

Abstract: An electrical system wherein the electrical conductive traces on the circuit boards are routed to achieve a balanced net to reduce noise caused by transmission line reflections. A trace (202,216,248,274) is routed from the source terminal (200,214,236,260) of the net to a balanced junction (204,218,238,288) wherein if there are an odd number of load terminals, or loads, the balanced junction is located at one of the loads (204,238). The remaining loads are grouped into branches wherein each branch includes an equal number of loads. A trace is routed between each of the loads of each branch to serially connect the loads of each branch together, or, a trace is routed from a center one of the branch loads to each of the remaining branch loads, forming subbranches. In an alternate embodiment, a balanced subbranch is developed. The balanced load is connected to a pseudo-balanced load, which further receives an equal number of branches. The 3 pseudo-balanced load is then connected to another pseudo-balanced load, which may also receive an equal number of branches. This pseudo-balanced load is connected to the source. In another alternative, two balanced subbranches have their balanced loads connected to a central balanced load. This balanced load may receive even further numbers of equal branches. The balanced load is connected to the source.

Abstract translation: 一种电气系统，其中电路板上的导电迹线被路由以实现平衡网以减少由传输线反射引起的噪声。 轨迹（202,216,248,274）从网络的源终端（200,214,236,260）路由到平衡结（204,218,238,288），其中如果存在奇数个负载终端或负载，则平衡结位于一个负载（204,238 ）。 剩余的负载被分组成分支，其中每个分支包括相等数目的负载。 轨迹在每个分支的每个负载之间路由，以将每个分支的负载串联连接在一起，或者，轨迹从分支负载的中心一个路由到每个剩余的分支负载，形成子分支。 在替代实施例中，开发了平衡分支。 平衡负载连接到伪平衡负载，其进一步接收相等数量的分支。 然后，3个伪平衡负载连接到另一个可以接收相等数量的分支的伪平衡负载。 该伪平衡负载连接到源。 在另一个替代方案中，两个平衡子分支具有连接到中心平衡负载的平衡负载。 这种平衡负载可以接收更多数量的相等分支。 平衡负载连接到源。

公开(公告)号：EP0428917A3

公开(公告)日：1991-10-23

申请号：EP90120911.4

申请日：1990-10-31

Applicant: Compaq Computer Corporation

Inventor： Hamid, Mustafa Ali ,  Thoma III, Roy E. ,  Thayer, John S.

IPC: G06F12/08

CPC classification number: G06F13/4243 ,  G06F12/0888

Abstract: A method for slowing down a high speed microprocessor with an internal cache to maintain compatibility with application software written for slower speed microprocessors. The internal cache of the processor is invalidated during the slowdown and the cache address comparison circuitry is directed to evaluate external addresses for a preset interval, preventing the processor from the accessing the cache, thereby slowing down the processor. The external address evaluation direction is released when a bus requesting device indicates a bus request during the slowdown, allowing the processor to respond to the bus request promptly to prevent possible latency problems from occurring, but still maintaining the processor in a halted state.

Abstract translation: 一种使用内部缓存降低高速微处理器的方法，以保持与为较慢速度微处理器编写的应用软件的兼容性。 处理器的内部高速缓存在减速期间无效，并且缓存地址比较电路用于以预设间隔评估外部地址，防止处理器访问高速缓存，从而减慢处理器的速度。 当总线请求设备在减速期间指示总线请求时，外部地址评估方向被释放，允许处理器迅速地响应总线请求，以防止发生可能的等待时间问题，但仍然使处理器处于停止状态。