High temperature performance capable gallium nitride transistor
    3.
    发明公开
    High temperature performance capable gallium nitride transistor 有权
    具有高温性能的氮化镓晶体管

    公开(公告)号:EP1973163A3

    公开(公告)日:2008-12-10

    申请号:EP08250197.4

    申请日:2008-01-16

    申请人: CREE, INC.

    摘要: A transistor device capable of high performance at high temperatures. The transistor comprises a gate having a contact layer that contacts the active region. The gate contact layer is made of a material that has a high Schottky barrier when used in conjunction with a particular semiconductor system (e.g., Group-III nitrides) and exhibits decreased degradation when operating at high temperatures. The device may also incorporate a field plate to further increase the operating lifetime of the device.

    摘要翻译: 一种能够在高温下实现高性能的晶体管器件。 晶体管包括具有接触有源区的接触层的栅极。 当与特定的半导体系统(例如III族氮化物)结合使用时,栅极接触层由具有高肖特基势垒的材料制成,并且当在高温下操作时表现出降低的退化。 该设备还可以包含场板以进一步增加设备的使用寿命。

    High Temperature Performance Capable Gallium Nitride Transistor
    7.
    发明公开
    High Temperature Performance Capable Gallium Nitride Transistor 有权
    具有高温性能的氮化镓晶体管

    公开(公告)号:EP2385558A3

    公开(公告)日:2013-08-21

    申请号:EP11176492.4

    申请日:2008-01-16

    申请人: Cree, Inc.

    摘要: A transistor device capable of high performance at high temperatures. The transistor comprises a gate having a contact layer that contacts the active region. The gate contact layer is made of a material that has a high Schottky barrier when used in conjunction with a particular semiconductor system (e.g., Group-III nitrides) and exhibits decreased degradation when operating at high temperatures. The device may also incorporate a field plate to further increase the operating lifetime of the device.

    摘要翻译: 一种能够在高温下实现高性能的晶体管器件。 晶体管包括具有接触有源区的接触层的栅极。 当与特定的半导体系统(例如III族氮化物)结合使用时,栅极接触层由具有高肖特基势垒的材料制成,并且当在高温下操作时表现出降低的退化。 该设备还可以包含场板以进一步增加设备的使用寿命。

    High voltage low current surface emitting LED
    8.
    发明公开
    High voltage low current surface emitting LED 审中-公开
    表面发射LED具有高电压和低电流

    公开(公告)号:EP2239776A3

    公开(公告)日:2015-04-01

    申请号:EP10159157.6

    申请日:2010-04-06

    申请人: Cree, Inc.

    IPC分类号: H01L25/075

    摘要: A monolithic LED chip (60) is disclosed comprising a plurality of junctions or sub-LEDs (62a-c) mounted on a submount (64). The sub-LEDs are serially interconnected such that the voltage necessary to drive the sub-LEDs is dependent on the number of serially interconnected sub-LEDs and the junction voltage of the sub-LEDs. Methods for fabricating a monolithic LED chip are also disclosed with one method comprising providing a single junction LED on a submount and separating the single junction LED into a plurality of sub-LEDs. The sub-LEDs are then serially interconnected such that the voltage necessary to drive the sub-LEDs is dependent on the number of the serially interconnected sub-LEDs and the junction voltage of the sub-LEDs.

    High Temperature Performance Capable Gallium Nitride Transistor
    9.
    发明公开
    High Temperature Performance Capable Gallium Nitride Transistor 有权
    Bei Hochtemperaturleistungsfähiger镓氮化物晶体管

    公开(公告)号:EP2385558A2

    公开(公告)日:2011-11-09

    申请号:EP11176492.4

    申请日:2008-01-16

    申请人: Cree, Inc.

    摘要: A transistor device capable of high performance at high temperatures. The transistor comprises a gate having a contact layer that contacts the active region. The gate contact layer is made of a material that has a high Schottky barrier when used in conjunction with a particular semiconductor system (e.g., Group-III nitrides) and exhibits decreased degradation when operating at high temperatures. The device may also incorporate a field plate to further increase the operating lifetime of the device.

    摘要翻译: 在高温下能够高性能的晶体管器件。 晶体管包括具有接触有源区的接触层的栅极。 当与特定的半导体系统(例如III族氮化物)结合使用时,栅极接触层由具有高肖特基势垒的材料制成,并且在高温下操作时表现出降低的降解。 该装置还可以包括场板以进一步增加装置的工作寿命。

    Low voltage diode with reduced parasitic resistance and method for fabricating
    10.
    发明公开
    Low voltage diode with reduced parasitic resistance and method for fabricating 有权
    具有降低的寄生电阻低电压二极管,和其制备方法

    公开(公告)号:EP1947700A3

    公开(公告)日:2010-01-13

    申请号:EP07254498.4

    申请日:2007-11-16

    申请人: CREE, INC.

    IPC分类号: H01L29/872 H01L21/329

    摘要: A method of making a diode begins by depositing an Al x Ga 1-x N nucleation layer on a SiC substrate, then depositing an n+ GaN buffer layer (112), an n- GaN layer (110), an Al x Ga 1-x N barrier layer (108), and an SiO 2 dielectric layer. A portion of the dielectric layer is removed and a Schottky metal (106) deposited in the void. The dielectric layer is affixed to the support layer with a metal bonding layer using an Au-Sn utectic wafer bonding process, the substrate is removed using reactive ion etching to expose the n+ layer, selected portions of the n+, n-, and barrier layers are removed to form a mesa diode structure on the dielectric layer over the Schottky metal (106); and an ohmic (114) contact is deposited on the n+ layer (112).