公开(公告)号：EP2315256B1

公开(公告)日：2015-04-08

申请号：EP11154411.0

申请日：2002-07-08

申请人： Cree, Inc.

发明人： Parikh, Primit ,  Mishra, Umesh

IPC分类号： H01L29/872 ,  H01L29/88

CPC分类号： H01L29/475 ,  H01L29/2003 ,  H01L29/872 ,  H01L29/88

公开(公告)号：EP2515339A3

公开(公告)日：2012-12-12

申请号：EP12171403.4

申请日：2005-04-21

申请人： Cree, Inc.

发明人： Wu, Yifeng ,  Parikh, Primit ,  Mishra, Umesh ,  Moore, Marcia

IPC分类号： H01L29/812 ,  H01L29/417 ,  H01L29/40

CPC分类号： H01L29/402 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/812

摘要： A transistor, comprises an active region; a source electrode (18) in electrical contact with the active region; a drain electrode (20) in electrical contact with the active region; and a gate (22) in electrical contact with the active region between the source and drain electrodes. A spacer layer (26) is provided over at least a portion of the region between the gate and the drain electrode and between the gate and the source electrode. A field plate (30) on the spacer layer is electrically isolated from the active region and gate by the spacer layer formed at least partially over the gate. The field plate is electrically connected to the source electrode by at least one conductive path (32), each of which at least one conductive path is formed on the spacer layer and covers less than all the topmost surface of the spacer layer between the gate and source electrode.

摘要翻译： 晶体管，包括有源区; 源电极（18），其与有源区电接触; 与有源区电接触的漏电极（20） 和与源电极和漏电极之间的有源区电接触的栅极（22）。 在栅极和漏极之间以及栅极和源极之间的区域的至少一部分上设置有间隔层（26）。 隔离层上的场板（30）通过至少部分地形成在栅极上方的隔离层与有源区和栅极电隔离。 场板通过至少一个导电路径（32）电连接到源电极，每个导电路径在间隔层上形成至少一个导电路径，并覆盖栅极和栅极之间的间隔层的全部最顶表面 源电极。

公开(公告)号：EP2312634A2

公开(公告)日：2011-04-20

申请号：EP11153385.7

申请日：2006-07-07

申请人： Cree, Inc.

发明人： Wu, Yifeng ,  Moore, Marcia ,  Parikh, Primit ,  Wisleder, Tim

IPC分类号： H01L29/778 ,  H01L21/338 ,  H01L29/207 ,  H01L29/40 ,  H01L29/20

摘要： A high electron mobility transistor (HEMT), comprises a buffer layer; a barrier layer on said buffer layer; a two dimensional electron gas (2DEG) at the interface between said buffer layer and said barrier layer; and a negative ion region in said barrier layer.

摘要翻译： 高电子迁移率晶体管（HEMT）包括缓冲层; 在所述缓冲层上的阻挡层; 在所述缓冲层和所述阻挡层之间的界面处的二维电子气（2DEG） 和在所述阻挡层中的负离子区域。

公开(公告)号：EP2270871A1

公开(公告)日：2011-01-05

申请号：EP10183607.0

申请日：2005-03-24

申请人： Cree, Inc.

发明人： Wu, Yifeng ,  Parikh, Primit ,  Mishra, Umesh ,  Moore, Marcia

IPC分类号： H01L29/778 ,  H01L29/06

CPC分类号： H01L29/402 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/7787

摘要： A transistor comprises a plurality of active semiconductor layers (16,18) and source and drain electrodes (20, 22) on the semiconductor layers. A gate (24) is formed between the source and drain electrodes and on the semiconductor layers. A spacer layer (26) covers at least part of the surface of the semiconductor layers between the gate and the drain, or covers at least part of the surface of the semiconductor layers between the gate and the source. A field plate (30) is formed on the spacer layer; and a conductive path (34,46) runs outside the area covered by the semiconductor layers, and between the field plate and the source electrode to electrically connect the field plate to the source electrode.

摘要翻译： 晶体管包括在半导体层上的多个有源半导体层（16,18）和源极和漏极（20,22）。 在源极和漏极之间以及半导体层上形成栅极（24）。 间隔层（26）覆盖栅极和漏极之间的半导体层的至少一部分表面，或者覆盖栅极和源极之间的半导体层的表面的至少一部分。 在间隔层上形成场板（30） 并且导电路径（34,46）延伸到由半导体层覆盖的区域的外部，并且在场板和源极之间，以将场板电连接到源电极。

公开(公告)号：EP2267784A2

公开(公告)日：2010-12-29

申请号：EP10187943.5

申请日：2002-07-23

申请人： Cree, Inc.

发明人： Parikh, Primit ,  Mishra, Umesh ,  Wu, Yifeng

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/7787 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/432 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

摘要： AlGaN/GaN HEMTs are disclosed having a thin AlGaN layer to reduce trapping and also having additional layers to reduce gate leakage and increase the maximum drive current. One HEMT according to the present invention comprises a high resistivity semiconductor layer 20 with a barrier semiconductor layer 18 on it. The barrier layer 18 has a wider bandgap than the high resistivity layer 20 and a 2DEG 22 forms between the layers. Source and drain contacts 13,14 contact the barrier layer 18, with part of the surface of the barrier layer 18 uncovered by the contacts 13,14. An insulating layer 24 is included on the uncovered surface of the barrier layer 18 and a gate contact 16 is included on the insulating layer 24. The insulating layer 24 forms a barrier to gate leakage current and also helps to increase the HEMT's maximum current drive; The invention also includes methods for fabricating HEMTs according to the present invention. In one method, the HEMT and its insulating layer are fabricated using metal-organic chemical vapor deposition MOCVD. In another method the insulating layer is sputtered onto the top surface of the HEMT in a sputtering chamber.

摘要翻译： 公开了具有薄AlGaN层的AlGaN / GaN HEMT，以减少陷阱并且还具有附加层以减少栅极泄漏并增加最大驱动电流。 根据本发明的一个HEMT包括其上具有阻挡半导体层18的高电阻率半导体层20。 阻挡层18具有比高电阻率层20更宽的带隙，并且在层之间形成2DEG 22。 源极和漏极触点13,14与阻挡层18接触，阻挡层18的一部分表面被触点13,14覆盖。 绝缘层24包括在阻挡层18的未覆盖表面上，并且在绝缘层24上包括栅极接触16.绝缘层24对栅极泄漏电流形成屏障并且还有助于增加HEMT的最大电流驱动; 本发明还包括用于制造根据本发明的HEMT的方法。 在一种方法中，使用金属有机化学气相沉积MOCVD制造HEMT及其绝缘层。 在另一种方法中，在溅射室中将绝缘层溅射到HEMT的顶表面上。

公开(公告)号：EP1947700A2

公开(公告)日：2008-07-23

申请号：EP07254498.4

申请日：2007-11-16

申请人： CREE, INC.

发明人： Parikh, Primit ,  Heikman, Sten

IPC分类号： H01L29/872 ,  H01L21/329

CPC分类号： H01L29/66143 ,  H01L29/2003 ,  H01L29/475 ,  H01L29/66212 ,  H01L29/872

摘要： A method of making a diode begins by depositing an Al x Ga 1-x N nucleation layer on a SiC substrate, then depositing an n+ GaN buffer layer, an n- GaN layer, an Al x Ga 1-x N barrier layer, and an SiO 2 dielectric layer. A portion of the dielectric layer is removed and a Schottky metal deposited in the void. The dielectric layer is affixed to the support layer with a metal bonding layer using an Au-Sn utectic wafer bonding process, the substrate is removed using reactive ion etching to expose the n+ layer, selected portions of the n+ , n-, and barrier layers are removed to form a mesa diode structure on the dielectric layer over the Schottky metal,; and an ohmic contact is deposited on the n+ layer.

摘要翻译： 一种制造二极管的方法开始于沉积基板的Al x上的SiC嘎1-X N成核层，然后沉积上的n-GaN层（110）的的Al x Ga 1- N + GaN缓冲层（112） ×N个势垒层（108），和SiO 2介电层。 介电层的一部分被除去并且在空隙沉积肖特基金属（106）。 该介电层被固定到用于Au-Sn系utectic晶片键合工艺的金属接合层的支撑层，所述基材是利用反应性离子蚀刻以露出n +层，n +的选定部分，正移除，并且势垒层 被去除，以形成在所述肖特基金属（106）的电介质层上的台面二极管结构; 和在欧姆（114）接触被沉积在n +层（112）上。

公开(公告)号：EP2312634B1

公开(公告)日：2019-12-25

申请号：EP11153385.7

申请日：2006-07-07

申请人： Cree, Inc.

发明人： Wu, Yifeng ,  Moore, Marcia ,  Parikh, Primit ,  Wisleder, Tim

IPC分类号： H01L29/778 ,  H01L21/338 ,  H01L29/207 ,  H01L29/40 ,  H01L29/20

公开(公告)号：EP1821344B1

公开(公告)日：2015-09-16

申请号：EP06126233.3

申请日：2006-12-15

申请人： Cree, Inc.

发明人： Saxler, Adam William ,  Wu, Yifeng ,  Parikh, Primit

IPC分类号： H01L29/778 ,  H01L29/201 ,  H01L21/335

CPC分类号： H01L29/7785 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/802

公开(公告)号：EP2538446A2

公开(公告)日：2012-12-26

申请号：EP12180744.0

申请日：2005-04-14

申请人： Cree, Inc.

发明人： Wu, Yifeng ,  Parikh, Primit ,  Mishra, Umesh ,  Moore, Marcia

IPC分类号： H01L29/778 ,  H01L29/06

CPC分类号： H01L29/404 ,  H01L29/2003 ,  H01L29/7787

摘要： A transistor (10) comprises an active region (18) having a channel and source (20) and drain (22) electrodes in contact with the active region. A gate (24, 124,142) is between the source and drain electrodes and on the active region. A plurality of field plates (30,42) is arranged on the active region, each extending toward the drain electrode, and each of which is isolated from the active region and from the others of the field plates. The topmost (42) of the field plates electrically is connected to the source electrode.

摘要翻译： 晶体管（10）包括具有沟道的有源区（18）和源极（20）以及与有源区接触的漏极（22）电极。 栅极（24,124,142）在源极和漏极之间以及有源区上。 多个场板（30,42）布置在有源区上，每个场板朝向漏电极延伸，并且每个场板与有源区域和场板中的其它区域隔离。 电场的最顶端（42）电连接到源电极。

公开(公告)号：EP2515339A2

公开(公告)日：2012-10-24

申请号：EP12171403.4

申请日：2005-04-21

申请人： Cree, Inc.

发明人： Wu, Yifeng ,  Parikh, Primit ,  Mishra, Umesh ,  Moore, Marcia

IPC分类号： H01L29/812 ,  H01L29/41

CPC分类号： H01L29/402 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/812

摘要： A transistor, comprises an active region; a source electrode (18) in electrical contact with the active region; a drain electrode (20) in electrical contact with the active region; and a gate (22) in electrical contact with the active region between the source and drain electrodes. A spacer layer (26) is provided over at least a portion of the region between the gate and the drain electrode and between the gate and the source electrode. A field plate (30) on the spacer layer is electrically isolated from the active region and gate by the spacer layer formed at least partially over the gate. The field plate is electrically connected to the source electrode by at least one conductive path (32), each of which at least one conductive path is formed on the spacer layer and covers less than all the topmost surface of the spacer layer between the gate and source electrode.