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    GROUP-III NITRIDE BASED HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH BARRIER/SPACER LAYER
    5.
    发明公开
    GROUP-III NITRIDE BASED HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH BARRIER/SPACER LAYER 有权
    具有阻挡层/间隔层的基于III族氮化物的高电子迁移率晶体管（HEMT）

    公开(公告)号：EP1390983A1

    公开(公告)日：2004-02-25

    申请号：EP02769655.8

    申请日：2002-04-11

    申请人： Cree, Inc. ,  The Regent of the University of California

    发明人： SMORCHKOVA, Ioulia, P. ,  WALUKIEWICZ, Wladyslaw ,  CHAVARKAR, Prashant ,  WU, Yifeng ,  KELLER, Stacia ,  MISHRA, Umesh

    IPC分类号： H01L29/778

    CPC分类号： H01L29/7783 ,  H01L29/2003

    摘要： A group III nitride based high electron mobility transistor (HEMT) (10) is disclosed that provides improved high frequency performance. One embodiment of the HEMT (10) comprises a GaN buffer layer (26), with an AlyGa1-yN (y=1 or y 1) layer (28) on the Gan buffer layer (26). An AlxGa1-xN (0≤x≤0.5) barrier layer (30) is on the AlyGa1-yN layer (28), opposite the GaN buffer layer (26), the AlyGa1-yN layer (28) having a higher Al concentration than that of the AlxGa1-xN barrirer layer (30). A preferred AlyGa1-yN layer (28) has y=1 or y≃1 and a preferred AlxGa1-xN barrier layer (30) has 0≤0.5. A 2DEG (38) forms at the interface between the GaN buffer layer (26) and the AlyGa1-yN layer (28). Respective source, drain and gate contacts (32, 34, 36) are formed on the AlxGa1-xN barrier layer (30). The HEMT (10) can also include a substrate (22) adjacent to the buffer layer (26), opposite the AlyGa1-yN layer (28) and a nucleation layer (24) can be included between the GaN buffer layer (26) and the substrate (22).

    摘要翻译： 公开了III族氮化物基高电子迁移率晶体管（HEMT）（10），其提供改进的高频性能。 HEMT（10）的一个实施例包括GaN缓冲层（26），在Gan缓冲层（26）上具有AlyGa1-yN（y = 1或y1）层（28）。 Al x Ga 1-x N（0≤x≤0.5）阻挡层（30）位于与GaN缓冲层（26）相对的Al y Ga 1-y N层（28）上，Al y Ga 1-y N层 AlxGa1-xN分枝层（30）的结构。 优选的AlyGa1-yN层（28）具有y = 1或y≥1，优选的Al x Ga 1-x N势垒层（30）具有0≤0.5。 2DEG（38）在GaN缓冲层（26）与AlyGa1-yN层（28）之间的界面处形成。 在Al x Ga 1-x N势垒层（30）上形成各自的源极，漏极和栅极接触（32,34,36）。 HEMT（10）还可以包括与AlyGa1-yN层（28）相对的与缓冲层（26）相邻的衬底（22），并且成核层（24）可以包括在GaN缓冲层（26）和 衬底（22）。

    GALLIUM NITRIDE BASED DIODES WITH LOW FORWARD VOLTAGE AND LOW REVERSE CURRENT OPERATION
    6.
    发明授权
    GALLIUM NITRIDE BASED DIODES WITH LOW FORWARD VOLTAGE AND LOW REVERSE CURRENT OPERATION 有权
    二极管的氮化镓以经营AT低正向电压和低反向功率

    公开(公告)号：EP1410445B1

    公开(公告)日：2011-07-06

    申请号：EP02798906.0

    申请日：2002-07-08

    申请人： CREE, INC.

    发明人： PARIKH, Primit ,  MISHRA, Umesh

    IPC分类号： H01L29/872 ,  H01L29/88

    CPC分类号： H01L29/475 ,  H01L29/2003 ,  H01L29/872 ,  H01L29/88

    摘要： New Group III based diodes are disclosed having a low on state voltage (Vf) and structures to keep reverse current (Irev) relatively low. One embodiment of the invention is Schottky barrier diode (10) made from the GaN material system in which the Fermi level (or surface potential) of is not pinned. The barrier potential (33) at the metal-to-semiconductor junction varies depending on the type of metal (16) used and using particular metals lowers the diode's Schottky barrier potential (33) and results in a Vf in the range of 0.1-0.3V. In another embodiment (40) a trench structure (45) is formed on the Schottky diodes semiconductor material (44) to reduce reverse leakage current and comprises a number of parallel, equally spaced trenches (46) with mesa regions (49) between adjacent trenches (46). A third embodiment of the invention provides a GaN tunnel diode with a low Vf resulting from the tunneling of electrons through the barrier potential (81), instead of over it. An embodiment of the tunnel diode (120) can also have a trench structure (121) to reduce reverse leakage current.

    WIDE BANDGAP TRANSISTORS WITH MULTIPLE FIELD PLATES
    7.
    发明公开
    WIDE BANDGAP TRANSISTORS WITH MULTIPLE FIELD PLATES 审中-公开
    对于有多个场板BIG BAND距离TRANSISTORS

    公开(公告)号：EP1751804A2

    公开(公告)日：2007-02-14

    申请号：EP05735109.0

    申请日：2005-04-14

    申请人： CREE, INC.

    发明人： WU, Yifeng ,  PARIKH, Primit ,  MISHRA, Umesh ,  MOORE, Marcia

    IPC分类号： H01L29/778 ,  H01L29/06

    摘要： A transistor (10) comprises an active region (18) having a channel and source (20) and drain (22) electrodes in contact with the active region. A gate (24, 124,142) is between the source and drain electrodes and on the active region. A plurality of field plates (30,42) is arranged on the active region, each extending toward the drain electrode, and each of which is isolated from the active region and from the others of the field plates. The topmost (42) of the field plates electrically is connected to the source electrode.