公开(公告)号：EP0222520B1

公开(公告)日：1993-03-10

申请号：EP86308026.3

申请日：1986-10-16

申请人： DATA GENERAL CORPORATION

发明人： Marshall, Peter G. ,  Feldstein, Robert

IPC分类号： G06F13/36 ,  G06F13/42

CPC分类号： G06F13/378 ,  G06F11/10 ,  G06F13/4243

公开(公告)号：EP0222520A3

公开(公告)日：1989-02-08

申请号：EP86308026.3

申请日：1986-10-16

申请人： DATA GENERAL CORPORATION

发明人： Marshall, Peter G. ,  Feldstein, Robert

IPC分类号： G06F13/36 ,  G06F13/42

CPC分类号： G06F13/378 ,  G06F11/10 ,  G06F13/4243

摘要： A computing system uses a system busy signal (SDBUSY) on its system bus to help control access to the bus. Each requester requiring access to the bus generates its internal request signal (SET REQ). One or more requesters can generate a request signal (SDREQX) on the bus when the system busy signal is not asserted (gate 74 and flip-flop 76). System busy is asserted along with the request signal(s) and remains asserted until all requesters which generated a request signal have gained access to the bus in order of priority. Bus access is enabled by a signal (PRIORITY) only when all higher priority request signals (SDREQ1-SDREQX-1) are false (gate 72). A freeze signal (DRVFREZ) is generated on the system bus during the address phase of an instruction and a wait signal is generated during each data transfer in the data phase of an instruction. These signals must be false before a requester with its request signal and priority signal tone can access the bus by putting an address signal thereon. The freeze signal may be generated by a memory control unit, a memory module or a requester.

公开(公告)号：EP0222520A2

公开(公告)日：1987-05-20

申请号：EP86308026.3

申请日：1986-10-16

申请人： DATA GENERAL CORPORATION

发明人： Marshall, Peter G. ,  Feldstein, Robert

IPC分类号： G06F13/36 ,  G06F13/42

CPC分类号： G06F13/378 ,  G06F11/10 ,  G06F13/4243

摘要： A computing system uses a system busy signal (SDBUSY) on its system bus to help control access to the bus. Each requester requiring access to the bus generates its internal request signal (SET REQ). One or more requesters can generate a request signal (SDREQX) on the bus when the system busy signal is not asserted (gate 74 and flip-flop 76). System busy is asserted along with the request signal(s) and remains asserted until all requesters which generated a request signal have gained access to the bus in order of priority. Bus access is enabled by a signal (PRIORITY) only when all higher priority request signals (SDREQ1-SDREQX-1) are false (gate 72). A freeze signal (DRVFREZ) is generated on the system bus during the address phase of an instruction and a wait signal is generated during each data transfer in the data phase of an instruction. These signals must be false before a requester with its request signal and priority signal tone can access the bus by putting an address signal thereon. The freeze signal may be generated by a memory control unit, a memory module or a requester.

摘要翻译： 计算系统在其系统总线上使用系统忙信号（SDBUSY）来帮助控制对总线的访问。 需要访问总线的每个请求者产生其内部请求信号（SET REQ）。 当系统忙信号未被置位（门74和触发器76）时，一个或多个请求者可以在总线上产生请求信号（SDREQX）。 系统忙与请求信号一起被断言，并保持断言，直到产生请求信号的所有请求者已经以优先级顺序获得对总线的访问。 只有当所有较高优先级请求信号（SDREQ1-SDREQX-1）都为假（门72）时，总线访问才被信号（PRIORITY）使能。 在指令的地址相位期间，在系统总线上产生冻结信号（DRVFREZ），并且在指令的数据阶段的每次数据传输期间产生等待信号。 在具有请求信号和优先级信号音的请求者可以通过在其上放置地址信号来访问总线之前，这些信号必须是假的。 冻结信号可以由存储器控制单元，存储器模块或请求者产生。